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PDF PIC24FJ64GA202 Data sheet ( Hoja de datos )
| Número de pieza | PIC24FJ64GA202 | |
| Descripción | 16-Bit Flash Microcontrollers | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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PIC24FJ128GA204 FAMILY
28/44-Pin, General Purpose, 16-Bit Flash Microcontrollers with
Cryptographic Engine, ISO 7816 and XLP Technology
Cryptographic Engine
• AES Engine with 128,192 or 256-Bit Key
• Supports ECB, CBC, OFB, CTR and
CFB128 modes
• DES/Triple DES (TDES) Engine: Supports
2-Key and 3-Key EDE or DED TDES
• Supports up to Three Unique Keys for TDES
• Programmatically Secure
• Pseudorandom Number Generator
• True Random Number Generator
• Non-Readable, On-Chip, OTP Key Storages
Extreme Low-Power Features
• Multiple Power Management Options for Extreme
Power Reduction:
- VBAT allows the device to transition to a
backup battery for the lowest power
consumption with RTCC
- Deep Sleep allows near total power-down
with the ability to wake-up on internal or
external triggers
- Sleep and Idle modes selectively shut down
peripherals and/or core for substantial power
reduction and fast wake-up
- Doze mode allows CPU to run at a lower
clock speed than peripherals
Memory
Analog
Peripherals
Extreme Low-Power Features (Continued)
• Alternate Clock modes allow On-the-Fly
Switching to a Lower Clock Speed for Selective
Power Reduction
• Extreme Low-Power Current Consumption for
Deep Sleep:
- WDT: 270 nA @ 3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current, 40 nA, 3.3V typical
Analog Features
• 10/12-Bit, 13-Channel Analog-to-Digital (A/D)
Converter:
- Conversion rate of 500 ksps (10-bit),
200 ksps (12-bit)
- Conversion available during Sleep and Idle
• Three Rail-to-Rail, Enhanced Analog Comparators
with Programmable Input/Output Configuration
• Three On-Chip Programmable Voltage References
• Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 13 channels
- Time measurement down to 100 ps resolution
- Operation in Sleep mode
Digital Peripherals
Device
PIC24FJ128GA204 128K 8K 44 13 3 13 6 6 2 3 4 Y 5 Y Y
PIC24FJ128GA202 128K 8K 28 10 3 10 6 6 2 3 4 N 5 Y Y
PIC24FJ64GA204
64K 8K 44 13 3 13 6 6 2 3 4 Y 5 Y Y
PIC24FJ64GA202
64K 8K 28 10 3 10 6 6 2 3 4 N 5 Y Y
2013-2014 Microchip Technology Inc.
DS30010038B-page 1
1 page  
Pin Diagrams (Continued)
44-Pin TQFP,
44-Pin QFN(1,2,3)
PIC24FJ128GA204 FAMILY
5V tolerant
RB9
RC6
RC7
RC8
RC9
VBAT
VCAP
RB10
RB11
RB12
RB13
1 33
2 32
3 31
4 30
5 29
6 PIC24FJXXXGA204 28
7 27
8 26
9 25
10 24
11 23
RB4
RA8
RA3
RA2
VSS
VDD
RC2
RC1
RC0
RB3
RB2
Legend:
Note 1:
2:
RPn represents remappable peripheral pins.
The back pad on QFN devices should be connected to VSS.
See Table 1 for complete pinout descriptions.
TABLE 1: PIC24FJXXGA204 PIN FUNCTION DESCRIPTIONS
Pin Function Pin Function
1 C1INC/C2INC/C3INC/RP9/SDA1/T1CK/CTED4/PMD3/CN21/RB9
23 AN4/C1INB/RP2/SDA2/T5CK/T4CK/CTED13/CN6/RB2
2 RP22/PMA1/PMALH/CN18/RC6
24 AN5/C1INA/RP3/SCL2/CTED8/CN7/RB3
3 RP23/PMA0/PMALL/CN17/RC7
25 AN10/RP16/PMBE1/CN8/RC0
4 RP24/PMA5/CN20/RC8
26 AN11/RP17/PMCS2/CN9/RC1
5 RP25/CTED7/PMA6/CN19/RC9
27 AN12/RP18/PMACK1/CN10/RC2
6 VBAT
28 VDD
7 VCAP
29 VSS
8 RP10/CTED11/PMD2/CN16/PGD2/RB10
30 OSCI/CLKI/C1IND/PMCS1/CN30/RA2
9 REFI/RP11/CTED9/PMD1/CN15/PGC2/RB11
31 OSCO/CLKO/C2IND/CN29/RA3
10 AN8/HLVDIN/RP12/PMD0/CN14/RB12
32 TDO/PMA8/CN34/RA8
11 AN7/C1INC/REFO/RP13/CTPLS/PMRD/PMWR/CN13/RB13
33 SOSCI/CN1/RPI4/RB4
12 TMS/PMA2/PMALU/CN36/RA10
34 SOSCO/SCLKI/CN0/RA4
13 TCK/PMA7/CN33/RA7
35 TDI/PMA9/CN35/RA9
14 CVREF/AN6/C3INB/RP14/PMWR/PMNEB/RTCC/CTED5/CN12/RB14
36 RP19/PMBE0/CN28/RC3
15 AN9/C3INA/RP15/T3CK/T2CK/CTED6/PMA14/CN11/PMCS/PMCS1/RB15 37 RP20/PMA4/CN25/RC4
16 AVSS/VSS
38 RP21/PMA3/CN26/RC5
17 AVDD
39 VSS
18 MCLR
40 VDD
19 CVREF+/VREF+/AN0/C3INC/CTED1/CN2/RA0
41 PGD3/RP5/ASDA1/PMD7/CN27/RB5
20 CVREF-/VREF-/AN1/C3IND/CTED2/CN3/RA1
42 PGC3/RP6/ASCL1/PMD6/CN24/RB6
21 AN2/CTCMP/C2INB/RP0/CN4/PGD1/RB0
43 RP7/CTED3/INT0/CN23/PMD5/RB7
22 AN3/C2INA/RP1/CTED12/CN5/PGC1/RB1
44 RP8/SCL1/CTED10/PMD4/CN22/RB8
Legend:
RPn represents remappable peripheral pins.
Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.
2013-2014 Microchip Technology Inc.
DS30010038B-page 5
5 Page 
PIC24FJ128GA204 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA204 FAMILY: 44-PIN DEVICES
Features
PIC24FJ64GA204
PIC24FJ128GA204
Operating Frequency
DC – 32 MHz
Program Memory (bytes) 64K 128K
Program Memory (instructions)
22,016
44,032
Data Memory (bytes)
8K
Interrupt Sources (soft vectors/
NMI traps)
71 (67/4)
I/O Ports
Ports A, B, C
Total I/O Pins
35
Remappable Pins
25 (24 I/Os, 1 Input only)
Timers:
Total Number (16-bit)
5(1)
32-Bit (from paired 16-bit timers)
2
Input Capture w/Timer Channels
6(1)
Output Compare/PWM Channels
6(1)
Input Change Notification Interrupt
35
Serial Communications:
UART
4(1)
SPI (3-wire/4-wire)
I2C™
3(1)
2
Digital Signal Modulator (DSM)
Yes
Parallel Communications (EPMP/PSP)
Yes
JTAG Boundary Scan
Yes
12-Bit SAR Analog-to-Digital
Converter (A/D) (input channels)
13
Analog Comparators
3
CTMU Interface
13 Channels
Resets (and Delays)
Core POR, VDD POR, VBAT POR, BOR, RESET Instruction,
MCLR, WDT, Illegal Opcode, REPEAT Instruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set
76 Base Instructions, Multiple Addressing Mode Variations
Packages
44-Pin TQFP and QFN
Cryptographic Engine
Supports AES with 128, 192 and 256-Bit Key, DES and TDES,
True Random and Pseudorandom Number Generator,
On-Chip OTP Storage
RTCC
Yes
Note 1: Peripherals are accessible through remappable pins.
2013-2014 Microchip Technology Inc.
DS30010038B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC24FJ64GA202.PDF ] | |
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