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Número de pieza PHPT60415NY
Descripción NPN high power bipolar transistor
Fabricantes NXP Semiconductors 
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PHPT60415NY
40 V, 15 A NPN high power bipolar transistor
27 May 2015
Product data sheet
1. General description
NPN high power bipolar transistor in a SOT669 (LFPAK56) Surface-Mounted
Device (SMD) power plastic package.
PNP complement: PHPT60415PY
2. Features and benefits
High thermal power dissipation capability
High temperature applications up to 175 °C
Reduced Printed Circuit Board (PCB) requirements comparing to transistors in DPAK
High energy efficiency due to less heat generation
AEC-Q101 qualified.
3. Applications
Power management
Load switch
Linear mode voltage regulator
Backlighting applications
Motor drive
Relay replacement
4. Quick reference data
Table 1.
Symbol
VCEO
IC
ICM
RCEsat
Quick reference data
Parameter
Conditions
collector-emitter
voltage
open base
collector current
peak collector current single pulse; tp ≤ 1 ms
collector-emitter
saturation resistance
IC = 15 A; IB = 1.5 A; tp ≤ 300 µs;
δ ≤ 0.02; Tamb = 25 °C; pulsed
Min Typ Max Unit
- - 40 V
- - 15 A
- - 30 A
- 28 40 mΩ
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PHPT60415NY pdf
NXP Semiconductors
PHPT60415NY
40 V, 15 A NPN high power bipolar transistor
103
Zth(j-a)
(K/W)
102 duty cycle = 1
0.75
0.33
0.5
0.2
10 0.1
0.05
0.02
1
0.01
aaa-016570
0
10-1
10-5
10-4
10-3
10-2
10-1
FR4 PCB, standard footprint
1
10 102 103
tp (ns)
Fig. 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
102 aaa-016571
Zth(j-a)
(K/W)
10
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
1 0.02 0.01
0
10-1
10-5
10-4
10-3
10-2
FR4 PCB, mounting pad for collector 6 cm2
10-1
1
10 102 103
tp (ns)
Fig. 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PHPT60415NY
Product data sheet
All information provided in this document is subject to legal disclaimers.
27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved
5 / 17

5 Page





PHPT60415NY arduino
NXP Semiconductors
PHPT60415NY
40 V, 15 A NPN high power bipolar transistor
12. Package outline
Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads
SOT669
L1
HD
E A A2 C
b2 c2
mounting
base
D1
L2
12 34
e b wA
1/2 e
X
c
E1
b3
b4
A
A1
C
detail X
(A3)
q
L
yC
Dimensions (mm are the original dimensions)
0
scale
5 mm
θ
8°
0°
Unit(1)
A A1 A2 A3 b b2 b3 b4 c c2 D(1) D1(1) E(1) E1(1) e H L L1
max 1.20 0.15 1.10
0.50 4.41 2.2
mm nom
0.25
min 1.01 0.00 0.95
0.35 3.62 2.0
0.9 0.25 0.30 4.10 4.20
0.7 0.19 0.24 3.80
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
5.0
4.8
3.3 6.2 0.85 1.3
1.27
3.1 5.8 0.40 0.8
Outline
version
References
IEC
JEDEC
JEITA
European
projection
SOT669
MO-235
L2 w y
1.3
0.25 0.1
0.8
sot669_po
Issue date
11-03-25
13-02-27
Fig. 14. Package outline LFPAK56; Power-SO8 (SOT669)
PHPT60415NY
Product data sheet
All information provided in this document is subject to legal disclaimers.
27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved
11 / 17

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