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PDF CS3524A Data sheet ( Hoja de datos )
| Número de pieza | CS3524A | |
| Descripción | Voltage Mode PWM Control Circuit | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CS3524A
Voltage Mode
PWM Control Circuit with
200 mA Output Drivers
The CS3524A PWM control circuit retains the same versatile
architecture of the industry standard CS3524 (SG3524) while adding
substantial improvements.
The CS3524 is pin−compatible with “non−A” versions, and in most
applications can be directly interchanged. The CS3524A, however,
eliminates many of the design restrictions which had previously
required additional external circuitry.
The CS3524A includes a precision 5.0 V reference trimmed to ±1%
accuracy (eliminating the need for potentiometer adjustments), an
error amplifier with an output voltage swing extending to 5.0 V, and a
current sense amplifier useful in either the ground or power supply
output lines. The uncommitted 60 V, 200 mA NPN output pair greatly
enhances the output drive capability.
The CS3524A features an undervoltage lockout circuit which
disables all internal circuitry (except the reference) until the input
voltage has risen to 8.0 V. This holds standby current low until
turn−on, and greatly simplifies the design of low power, off−line
supplies. The turn−on circuit has approximately 600 mV of hysteresis
for jitter free activation.
Other improvements include a PWM latch that insures freedom
from multiple pulsing within a period, even in noisy environments;
logic to eliminate double pulsing on a single output, a 200 ns external
shutdown capability, and automatic thermal protection from excessive
chip temperature. The oscillator circuit is usable to 500 kHz and is
easier to synchronize with an external clock pulse.
Features
• Precision Reference Internally Trimmed to ±1%
• Current Limit
• Undervoltage Lockout
• Start−Up Supply Current < 4.0 mA
• Output to 200 mA
• 60 V Output Capability
• Wide Common−Mode Input Range for Error and Current Limit
Amplifiers
• PWM Latch Insures Single Pulse per Period
• Double Pulse Suppression
• 200 ns Shutdown
• Guaranteed Frequency
• Thermal Shutdown
http://onsemi.com
16
1
DIP−16
N SUFFIX
CASE 648
MARKING
DIAGRAMS
16
CS3524A
AWLYYWW
1
16
1
SO−16L
DW SUFFIX
CASE 751G
16
CS3524A
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
EA−
EA+
SYNC
ISENSE+
ISENSE−
RT
CT
GND
VREF
VIN
EB
VOUTB
VOUTA
EA
SHUTDOWN
COMP
ORDERING INFORMATION
Device
Package
Shipping
CS3524AGN16
DIP−16 25 Units/Rail
CS3524AGDW16
CS3524AGDWR16
SO−16L 46 Units/Rail
SO−16L 1000 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 4
1
Publication Order Number:
CS3524A/D
1 page  
CS3524A
10
9
8 TA = −55°C
7 TA = 25°C
6 TA = 125°C
5
4
3
2
1
Note: Outputs off. RT = ∞
0 0 10 20 30 40 50
Supply Voltage VIN (V)
Figure 4. Quiescent Supply Current vs. Supply
Voltage Over Temperature
20 Output at
15 VOA or VOB
10
5 VIN = 20 V
0
RL = 2 kΩ
TA = 25°C
5
4
3
Input at VOB
2
1
0
Note: Minimum input pulse width to latch is 200 ns.
0123
Delay Time (μs)
Figure 5. Shutdown Delay from PWM Comparator
1M
100 k
1
2
3
VIN = 20 V
TA = 25°C
4
10 k 5
1. CT = 1.0 nF
1 k 2. CT = 3.0 nF
3. CT = 10 nF
4. CT = 30 nF
100 5. CT = 100 nF
12
5
f
[
1.15
RTCT
10 20
50 100
Timing Resistor, RT (kΩ)
Figure 6. Oscillator Frequency vs. Timing
Components Resistor Over Timing Capacitance
10
VIN = 20 V
5.0
RT = 2700 Ω
TA = 25°C
2.0
1.0
0.5
0.2 Note: Dead time = osc output
pulse width plus output delay
0.11 2
5 10 20
50 100
Timing Capacitor, CT (nF)
Figure 7. Output Dead Time vs. Timing Capacitor
Value
Output at COMP
6
5
4
3
2
Overdrive
1255000%%%%
1
0
0.2
Input at ISENSE+
VIN = 20 V, TA = 25°C
0.1
EA+ = VREF
ISENSE− = GND
0
012 34
Delay Time (μs)
Figure 8. Current Limit Amplifier Delay
20
15 VIN = 20 V
10
RL = 2.0 kΩ
TA = 25°C
5 Output at
0 VOA or VOB
1.0
0.5 Input at
Shutdown
0
Note: Minimum input pulse
width to latch is 200 ns.
01 2 3
Delay Time (μs)
Figure 9. Turn−Off Delay from Shutdown
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CS3524A.PDF ] | |
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