PDF AX8052F100 Data sheet ( Hoja de datos )

Número de pieza	AX8052F100
Descripción	Ultra-Low Power Microcontroller
Fabricantes	ON Semiconductor
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No Preview Available ! AX8052F100 Ultra-Low Power Microcontroller OVERVIEW The AX8052F100 is a single chip ultra−lowpower microcontroller primarily for use in radio applications. The AX8052F100 contains a high speed microcontroller compatible to the industry standard 8052 instruction set. It contains 64 kBytes of FLASH and 8.25 kBytes of internal SRAM. The AX8052F100 features 3 16−bit general purpose timers with SD capability, 2 output compare units for generating PWM signals, 2 input compare units to record timings of external signals, 2 16−bit wakeup timers, a watchdog timer, 2 UARTs, a Master/Slave SPI controller, a 10−bit 500 kSample/s A/D converter, 2 analog comparators, a temperature sensor, a 2 channel DMA controller, and a dedicated AES crypto controller. Debugging is aided by a dedicated hardware debug interface controller that connects using a 3−wire protocol (1 dedicated wire, 2 shared with GPIO) to the PC hosting the debug software. www.onsemi.com 1 28 QFN28 5x5, 0.5P CASE 485EH ORDERING INFORMATION Device Type Qty AX8052F100−2−TA05 Tape & Reel 500 AX8052F100−2−TW30 Tape & Reel 3,000 Features Ultra−low Power Microcontroller • QFN28 Package • Supply Range 1.8 V − 3.6 V • −40°C to 85°C • Ultra−low Power Consumption: ♦ CPU Active Mode 150 mA/MHz ♦ Sleep Mode with 256 Byte RAM Retention and Wake−up Timer running 850 nA ♦ Sleep Mode 4 kByte RAM Retention and Wake−up Timer running 1.5 mA ♦ Sleep Mode 8 kByte RAM Retention and Wake−up Timer running 2.2 mA AX8052 Core • Industry Standard 8052 Instruction Set • High Performance Core, most Instructions Require only 1 Clock per Instruction Byte • 20 MIPS Memory • 64 kByte FLASH 100,000 Erase Cycles 10 Year Data Retention • 8.25 kByte RAM • High Performance Memory Crossbar Clocking • Four Clock Sources ♦ On−chip 20 MHz RC−oscillator ♦ 10 kHz/640 Hz Ultra−low−power RC−oscillator ♦ Fast Crystal Oscillator ♦ Low Power Tuning Fork Crystal Oscillator • Fully Automatic Calibration of On−chip RC Oscillators to a Reference Clock • Clock Monitor can Detect Failures of the Main Clock and Switch to the On−chip Fast RC Oscillator • Dual DPTR for High Speed Memory Chips • 22 Interrupt Vectors • Watchdog Power Modes Debugger • Three−wire (1 dedicated, 2 shared with GPIO Pins) Debugger Interface • True Hardware Debugger with Breakpoints and Single Stepping Support • User Programmable 64−bit Key to restrict Debugging to Authorized Personnel • DebugLink Interface allows “printf” Style Debugging without utilizing a UART or GPIO Pins • Standby, Sleep and Deep Sleep Power Modes for Very Low Idle Power Consumption • On−chip Power−on−Reset and Brown−out Detection • Unrestricted Operation from 1.8 V − 3.6 V VDD_IO 16−bit Wakeup Timer • Two Counting Registers • Four Event Registers Allow Flexible Wakeup and Software Schedules © Semiconductor Components Industries, LLC, 2016 May, 2016 − Rev. 3 1 Publication Order Number: AX8052F100/D 1 page AX8052F100 Alternate Pin Functions GPIO Pins are shared with dedicated Input/Output signals of on−chip peripherals. The following table lists the available functions on each GPIO pin. Table 2. ALTERNATE PIN FUNCTIONS GPIO PA0 T0OUT PA1 T0CLK PA2 OC0 PA3 T1OUT PA4 T1CLK PA5 IC0 PB0 U1TX PB1 U1RX PB2 IC0 PB3 OC0 PB4 U0TX PB5 U0RX PB6 DBG_DATA PB7 DBG_CLK PC0 SSEL PC1 SSCK PC2 SMOSI PC3 SMISO PR0 RSEL PR1 RSYSCLK PR2 RCLK PR3 RMISO PR4 RMOSI PR5 RIRQ Alternate Functions IC1 ADC0 OC1 ADC1 U1RX ADC2 ADC3 COMPO0 ADC4 U1TX ADC5 IC1 EXTIRQ0 OC1 T2OUT T2CLK EXTIRQ1 T1CLK T1OUT T0OUT T0CLK U0TX U0RX EXTIRQ0 COMPO1 COMPO0 XTALP XTALN COMPI00 LPXTALP LPXTALN COMPI10 DSWAKE www.onsemi.com 5 5 Page AX8052F100 CIRCUIT DESCRIPTION The AX8052F100 is a single chip ultra−lowpower microcontroller primarily for use in radio applications. The AX8052F100 contains a high speed microcontroller compatible to the industry standard 8052 instruction set. It contains 64 kBytes of FLASH and 8.25 kBytes of internal SRAM. The AX8052F100 features 3 16−bit general purpose timers with SD capability, 2 output compare units for generating PWM signals, 2 input compare units to record timings of external signals, 2 16−bit wakeup timers, a watchdog timer, 2 UARTs, a Master/Slave SPI controller, a 10−bit 500 kSample/s A/D converter, 2 analog comparators, a temperature sensor, a 2 channel DMA controller, and a dedicated AES crypto controller. Debugging is aided by a dedicated hardware debug interface controller that connects using a 3−wire protocol (1 dedicated wire, 2 shared with GPIO) to the PC hosting the debug software. The system clock that clocks the microcontroller, as well as peripheral clocks, can be selected from one of the following clock sources: the crystal oscillator, an internal high speed 20 MHz oscillator, an internal low speed 640 Hz/10 kHz oscillator, or the low frequency crystal oscillator. Pre−scalers offer additional flexibility with their programmable divide by a power of two capability. To improve the accuracy of the internal oscillators, both oscillators may be slaved to the crystal oscillator. AX8052F100 can be operated from a 1.8 V to 3.6 V power supply over a temperature range of −40°C to 85°C. The AX8052F100 features make it an ideal interface for integration into various battery powered SRD solutions such as ticketing or as transceiver for telemetric applications e.g. in sensors. Microcontroller The AX8052F100 microcontroller core executes the industry standard 8052 instruction set. Unlike the original 8052, many instructions are executed in a single cycle. The system clock and thus the instruction rate can be programmed freely from DC to 20 MHz. Memory Architecture The AX8052F100 Microcontroller features the highest bandwidth memory architecture of its class. Figure 4 shows the memory architecture. Three bus masters may initiate bus cycles: • The AX8052 Microcontroller Core • The Direct Memory Access (DMA) Engine • The Advanced Encryption Standard (AES) Engine Bus targets include: • Two individual 4 kBytes RAM blocks located in X address space, which can be simultaneously accessed and individually shut down or retained during sleep mode • A 256 Byte RAM located in internal address space, which is always retained during sleep mode • A 64 kBytes FLASH memory located in code space. • Special Function Registers (SFR) located in internal address space accessible using direct address mode instructions • Additional Registers located in X address space (X Registers) The upper half of the FLASH memory may also be accessed through the X address space. This simplifies and makes the software more efficient by reducing the need for generic pointers. NOTE: Generic pointers include, in addition to the address, an address space tag. SFR Registers are also accessible through X address space, enabling indirect access to SFR registers. This allows driver code for multiple identical peripherals (such as UARTs or Timers) to be shared. The 4 word × 16 bit fully associative cache and a pre−fetch controller hide the latency of the FLASH. www.onsemi.com 11 11 Page

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