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PDF CMX7031 Data sheet ( Hoja de datos )
| Número de pieza | CMX7031 | |
| Descripción | The Two-Way Radio Processor | |
| Fabricantes | Consumer Microcircuits Limited | |
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CMX7031/CMX7041
CML Microcircuits
The Two-Way Radio
COMMUNICATION SEMICONDUCTORS
Processor
D/7031/41_FI1.x/13 July 2013
DATASHEET
Provisional Issue
7031/7041 FI-1.5: Baseband Audio and Data Processor with Auxiliary System
Clocks, ADCs and DACs for use in Analogue Radio Systems
Features
Concurrent Audio/Signalling/Data Operations
Full Audio-band Processing:
Pre and De-emphasis, Compandor,
Scrambler and Selectable 2.55/3.0 kHz Filters
2 x RF Synthesisers (CMX7031 only)
Inband Signalling: Selcall, DTMF, NOAA NWR
3 x Analogue Inputs (Mic or Discriminator)
2 x Auxiliary ADCs and 4 x Auxiliary DACs
C-BUS Serial Interface to Host µController
Low-power (3.0V to 3.6V) Operation
Available in 64-pin, 48-pin LQFP and VQFN
Packages
Selectable Audio Processing Order
MSK/FFSK Data Modem with Packet or Free-
format Modes with FEC, CRC, Interleaving and
Scrambling
Enhanced DSC Modem for Marine
Applications, offering support for DSC
expansion sequences and transmission of
continuous distress signals
Sub-Audio Signalling: CTCSS, DCS, XTCSS
Tx Outputs for Single, Two-Point or I/Q Mod.
559bps PSK Modulator
2 x Auxiliary System Clock Outputs
Flexible Powersave Modes
DAC outputs
ADC inputs
3.0V to 3.6V
Modulator
Discriminator
RF
RF Synthesiser 1
RF Synthesiser 2
CMX7031 only
GPIO
System Clock 1
System Clock 2
Reference Clock
CMX7031 / CMX7041
The Two-Way Radio Processor
Built on FirmASIC® technology
C-BUS
Host
µC
This document contains:
Datasheet
User
Manual
1. Brief Description
The CMX7031/CMX7041 FI 1.5 is a full-function, half-duplex, audio, signalling and data processor IC. This
makes it a suitable device for both the leisure radio markets (FRS, MURS, PMR446 and GMRS) and for
professional radio products (PMR/LMR, Marine and Trunking) with or without signalling and data facilities.
The device utilises CML’s proprietary FirmASIC component technology. On-chip sub-systems are
configured by a Function Image™: this is a data file that is uploaded during device initialisation and defines
the device’s function and feature set. The Function Image™ can be loaded automatically from an external
EEPROM or from a host µController over the built-in C-BUS serial interface. The device’s functions and
features can be enhanced by subsequent Function Image™ releases, facilitating in-the-field upgrades.
This document refers specifically to the features provided by Function Image™ 1.5.
Continued…
2013 CML Microsystems Plc
1 page  
The Two-Way Radio Processor
CMX7031/CMX7041
Table 12 Data Block Formatting Types......................................................................................... 48
Table 13 Maximum Data Transfer Latency................................................................................... 49
Table 14 C-BUS Registers ............................................................................................................ 64
Figure
Page
Figure 1 Block Diagram................................................................................................................... 8
Figure 2 CMX7031 Recommended External Components........................................................... 12
Figure 3 CMX7041 Recommended External Components........................................................... 13
Figure 4 CMX7031 Power Supply Connections and De-coupling................................................. 15
Figure 5 CMX7041 Power Supply Connections and De-coupling................................................. 16
Figure 6 C-BUS Transactions ....................................................................................................... 20
Figure 7 FI Loading from Host ...................................................................................................... 23
Figure 8 FI Loading from EEPROM .............................................................................................. 24
Figure 9 Signal Routing................................................................................................................. 26
Figure 10 Rx 12.5kHz Channel Audio Filter Frequency Response............................................... 29
Figure 11 Rx 25kHz Channel Audio Filter Frequency Response.................................................. 29
Figure 12 De-emphasis Curve for TIA/EIA-603 Compliance ........................................................ 30
Figure 13 Tx Channel Audio Filter Response and Template (ETSI)............................................. 31
Figure 14 Tx Channel Audio Filter Response and Template (TIA) ............................................... 32
Figure 15 Audio Frequency Pre-emphasis.................................................................................... 33
Figure 16 Expandor Transient Response ..................................................................................... 35
Figure 17 Compressor Transient Response ................................................................................. 35
Figure 18 Low Pass Sub-Audio Band Filter for CTCSS and DCS ................................................ 36
Figure 19 Modulating Waveforms for 1200 and 2400 Baud MSK/FFSK Signals.......................... 46
Figure 20 DSC Format .................................................................................................................. 50
Figure 21 DSC Character Format ................................................................................................. 51
Figure 22 Expanded DSC Format................................................................................................. 52
Figure 23 AuxADC IRQ Operation ................................................................................................ 56
Figure 24 Example RF Synthesiser Components for a 512MHz Receiver ................................... 57
Figure 25 Single RF Channel Block Diagram ............................................................................... 58
Figure 26 Digital Clock Generation Schemes ............................................................................... 61
Figure 27 Level Adjustments......................................................................................................... 63
Figure 28 C-BUS Timing ............................................................................................................... 79
Figure 29 Mechanical Outline of 64-pin VQFN (Q1) ..................................................................... 80
Figure 30 Mechanical Outline of 64-pin LQFP (L9)....................................................................... 80
Figure 31 Mechanical Outline of 48-pin VQFN (Q3) ..................................................................... 81
Figure 32 Mechanical Outline of 48-pin LQFP (L4)....................................................................... 81
1.1. History
Version
13
12
Changes
Added support for DSC expansion sequences (section 7.11), minor modification
to the Status ($C6) register b7 (section 9.1.21) and new bit definition in the
Programming Register (section 9.2.1)
Updated RAMDAC description in section 9.1.4
Function Image Updates (section 9.3) updated
Added SPI port descriptive text in section 7.4.1 and other minor corrections.
Date
17.7.13
27.10.11
2013 CML Microsystems Plc
Page 5
D/7031/41_FI1.x/13
5 Page 
The Two-Way Radio Processor
CMX7031/CMX7041
CMX7031 CMX7041
64-pin
48-pin
Q1/L9
Q3/L4
52 45
53 -
54 46
55 47
56 48
57 -
58 1
59 2
60 3
61 4
62 5
63 6
64 7
EXPOSED EXPOSED
METAL PAD METAL PAD
Pin
Name
DVSS
-
SCLK
SYSCLK2
CSN
-
EPSI
EPSCLK
EPSO
EPSCSN
BOOTEN1
BOOTEN2
DVSS
SUBSTRATE
Type
Description
PWR Digital Ground.
NC Reserved – do not connect this pin.
IP C-BUS: The C-BUS serial clock input from the µC.
OP Synthesised Digital System Clock Output 2.
IP
C-BUS: The C-BUS chip select input from the µC - there is
no internal pullup on this input.
NC Reserved – do not connect this pin.
OP EEPROM Serial Interface: SPI bus Output.
OP EEPROM Serial Interface: SPI bus Clock.
IP+PD EEPROM Serial Interface: SPI bus Input.
OP EEPROM Serial Interface: SPI bus Chip Select.
IP+PD
Used in conjunction with BOOTEN2 to determine the
operation of the bootstrap program.
IP+PD
Used in conjunction with BOOTEN1 to determine the
operation of the bootstrap program.
PWR Digital Ground.
On this device, the central metal pad (which is exposed on
Q1 & Q3 packages only) may be electrically unconnected or,
~ alternatively, may be connected to Analogue Ground (AVss).
No other electrical connection is permitted.
Notes:
IP
OP
BI
TS OP
PWR
NC
=
=
=
=
=
=
Input (+ PU/PD = internal pullup/pulldown resistor)
Output
Bidirectional
3-state Output
Power Connection
No Connection - should NOT be connected to any signal.
3.1. Signal Definitions
Signal
Name
AVDD
DVDD
RFVDD
CPVDD
VDEC
VBIAS
AVSS
DVSS
RFVSS
Table 1 Definition of Power Supply and Reference Voltages
Pins
AVDD
DVDD
RFVDD
CPVDD
VDEC
VBIAS
AVSS
DVSS
RFVSS
Usage
Power supply for analogue circuits
Power supply for digital circuits
Power supply for RF synthesiser circuits
Power supply for RF charge pump
Power supply for core logic, derived from DVDD by on-chip regulator
Internal analogue reference level, derived from AVDD
Ground for all analogue circuits
Ground for all digital circuits
Ground for all RF circuits
2013 CML Microsystems Plc
Page 11
D/7031/41_FI1.x/13
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CMX7031.PDF ] | |
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