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PDF ESD7504 Data sheet ( Hoja de datos )
| Número de pieza | ESD7504 | |
| Descripción | TVS Diode ( Rectifier ) | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ESD7504 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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ESD7504
Transient Voltage
Suppressors
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD7504 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines such as USB 3.0.
Features
• Low Capacitance (0.55 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• USB 3.0
• eSATA 1.0/2.0/3.0
• HDMI 1.3/1.4
• Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15 kV
±15 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
http://onsemi.com
UDFN10
CASE 517BB
MARKING
DIAGRAM
4E MG
G
4E = Specific Device Code (tbd)
M = Date Code
G = Pb−Free Package
(*Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
N/C N/C GND N/C N/C
10 9 8 7 6
12 3 4 5
I/O I/O GND I/O I/O
I/O I/O I/O I/O
Pin 1 Pin 2 Pin 4 Pin 5
Pins 3, 8
Note: Common GND − Only Minimum of 1 GND connection required
=
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2014
March, 2014 − Rev. 0
1
ORDERING INFORMATION
Device
ESD7504MUTAG
Package
UDFN10
(Pb−Free)
Shipping
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
ESD7504/D
1 page  
ESD7504
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
ESD7504
ESD7L5.0
StdA_SSTX−
D−
GND_DRAIN
D+
StdA_SSRX+
Figure 7. USB3.0 Layout Diagram
GND
StdA_SSRX−
Black = Top layer
Red = Other layer
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
♦ In USB 3.0 applications, the ESD protection device
should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes as shown in Figure 8.
• Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
Figure 8. USB 3.0 Connection Diagram
http://onsemi.com
5
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| PDF Descargar | [ Datasheet ESD7504.PDF ] | |
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