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PDF AN30182A Data sheet ( Hoja de datos )
| Número de pieza | AN30182A | |
| Descripción | 600mA Synchronous DC-DC Step Down Regulator | |
| Fabricantes | Panasonic | |
| Logotipo |  |
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AN30182A
600mA Synchronous DC-DC Step Down Regulator (2ch)
300mA LDO Regulator (6ch)
Multi Power Supply (High Efficiency Power LSI)
FEATURES
z High-Speed Response DC-DC Step Down Regulator
Circuit that employs Hysteretic System
z DC-DC Step Down Regulator : 2-ch
Input voltage Range VBAT :2.5V to 5.5V
DVDD : 1.7V to 3.0V
Output voltage Range 0.8 V to 2.4 V
Up to 600 mA Output Current
z LDO Regulator : 6-ch
Input voltage Range VBAT :2.5V to 5.5V
DVDD : 1.7V to 3.0V
Output voltage Range 1.0 V to 3.3 V
Up to 300 mA Output Current
z I2C control (2-slave address selectable)
z 25 pin Wafer Level Chip Size Package (WLCSP)
(Size : 2.15 mm × 2.15 mm, 0.4 mm Pitch)
DESCRIPTION
AN30182A is a multi power supply LSI which has High-
Speed Response DC-DC Step Down Regulators (2-ch)
and LDO Regulators (6-ch).
By this DC-DC system, when load current charges
suddenly, it responds at high speed and minimizes the
changes of output voltage.
Since it is possible to use capacitors with small
capacitance and it is unnecessary to add external parts
for system phase compensation, this IC realizes
downsizing of set and reducing in the number of external
parts.
The output DC of each power supply is variable by I2C
control.
APPLICATIONS
Mobile phone, Portable appliance, etc
SIMPLIFIED APPLICATION
DVDD
0.1µF
DDVBAT2 DDVBAT1
VB VIN2
4.7µF 4.7µF
4.7µF 4.7µF
SDA
SCL
ASEL
VLDO4
1µF
VLDO5
1µF
AN30182A
LX1
FB1
DDGND1
LX2
FB2
DDGND2
1µH
DCDCOUT1
4.7µF
DCDCOUT2
1µH
4.7µF
VLDO1
1µF
VLDO2
1µF
VLDO6
VLDO3
1µF
VREG REF RESET LDO1ON AGND
1µF 1µF
1µF
Notes) This application circuit is an example. The operation
of mass production set is not guaranteed. You should
perform enough evaluation and verification on the
design of mass production set. You are fully
responsible for the incorporation of the above
application circuit and information in the design of
your equipment.
Publication date: October 2012
1
EFFICIENCY CURVE
100
90
80
70
60
50
40
30
20
10
0
1
AN30182A DCDC1 Efficiency
Vout=0.8V
Vout=1.2V
Vout=1.8V
Vout=2.4V
10 100
Load Current [mA]
1000
Condition )
DDVBAT1 = DDVBAT2 = VB = VIN2 = 3.7V
Lo = 1.0 µH, Cout = 4.7 µF
Vout=0.8 , 1.2 , 1.8 , 2.4V
Ver. BEB
1 page  
AN30182A
ELECRTRICAL CHARACTERISTICS (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.7V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Parameter
Symbol
Conditions
Limits
Unit Notes
Min Typ Max
[ LDO1 – 6 ( Normal Mode ) ] (LDO Regulator)
Output voltage
VLDO
ILDO = – 150 mA
Vout = 1.85 V setting
1.803 1.850 1.897 V —
Output current
Load regulation
Line regulation
ILDO
DVLDO
VLDOLR
—
Δ ILDO = – 10 μA → – 150 mA
VB = 3.1 V → 4.5 V
ILDO = – 150 mA
Vout = 1.85 V setting
300
–5
– 10
—
20
0
— mA —
50 mV —
10 mV —
Short-circuit current
ISTLDO
VB = 3.7 V
VLDO = 0 V
35 100 255 mA —
[ LDO1 – 6 ( Power Save Mode ) ] (LDO Regulator)
Output voltage
VLDOPS
ILDO = – 5 mA
Vout = 1.85 V setting
1.803 1.850 1.897 V —
Output current
ILDOPS — 10 — — mA —
Load regulation
DVLDOPS Δ ILDO = – 10 μA → – 5 mA
– 5 20
50 mV —
Line regulation
VB = 3.1 V → 4.5 V
VLDOLRPS ILDO = – 5 mA
Vout = 1.85 V setting
– 25 0
25 mV —
5 Ver. BEB
5 Page 
APPLICATION INFORMATION (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.1V to 4.5V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Parameter
Symbol
Conditions
[ I2C bus (Bus line specifications) (continued) ]
Capacitive load for each bus line
Noise margin at the Low-level for
each connected device
Noise margin at the High-level for
each connected device
Cb
VnL
VnH
—
—
—
*2 : Checked by design, not production tested.
*3 : Checked by design, not production tested.
The timing of Fast-mode devices in I2C-bus is specified as the following.
All values referred to VIHmin and VILmax level.
AN30182A
Reference values
Unit Notes
Min Typ Max
—
0.1 ×
VDVDD
0.2 ×
VDVDD
—
—
—
400
pF
*2
*3
—
V
*2
*3
—
V
*2
*3
SDA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
SCL
S
tHD;STA
tHD;DAT
S : START condition
Sr : Repeat START condition
P : STOP condition
tHIGH
tSU;STA
Sr
tSP tr tBUF
tSU;STO
P
S
11 Ver. BEB
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AN30182A.PDF ] | |
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