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PDF PUSB3AB4 Data sheet ( Hoja de datos )

Número de pieza PUSB3AB4
Descripción ESD protection
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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PUSB3AB4
ESD protection for ultra high-speed interfaces
Rev. 1 — 25 August 2015
Objective data sheet
1. Product profile
1.1 General description
The device is designed to protect high-speed interfaces such as SuperSpeed USB 3.1 at
10 Gbps, High-Definition Multimedia Interface (HDMI), DisplayPort, external Serial
Advanced Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS)
interfaces against ElectroStatic Discharge (ESD).
The device includes a high-level ESD protection diode structure protecting sensitive
transmitters and receivers for ultra high-speed signal lines. The device is encapsulated in
a leadless small DFN2510A-10 (SOT1176-1) plastic package.
All signal lines are protected by a special diode configuration offering ultra low line
capacitance of only 0.2 pF maximum. These diodes utilize a snapback structure in order
to provide protection to downstream components from ESD voltages up to 15 kV contact
exceeding IEC 61000-4-2, level 4.
1.2 Features and benefits
System-level ESD protection for USB 2.0 and SuperSpeed USB 3.1 at 10 Gbps,
HDMI, DisplayPort, eSATA and LVDS
Line capacitance of only 0.2 pF maximum for each channel
Outstanding system protection: extremely deep snapback combined with dynamic
resistance of only 0.4 .
All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of 15 kV exceeding IEC 61000-4-2, level 4
Matched 0.5 mm trace spacing
Signal lines with 0.05 pF matching capacitance between signal pairs
Design-friendly ‘pass-through’ signal routing
1.3 Applications
The device is designed for high-speed receiver and transmitter port protection:
Smartphones, tablet computers, Mobile Internet Devices (MID) and portable devices
TVs and monitors
DVD recorders and players
Notebooks, main board graphic cards and ports
Set-top boxes and game consoles

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PUSB3AB4 pdf
NXP Semiconductors
9. Soldering
PUSB3AB4
ESD protection for ultra high-speed interfaces
Footprint information for reflow soldering of DFN2510A-10 package
SOT1176-1
Hx
Hy Ay By
C
0.05
D P 0.05
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
solder resist
Dimensions in mm
P Ay By
C
0.5 1.25 0.3 0.475
D
0.2
Hx
2.45
Hy
1.5
Remark:
Stencil of 75 μm is recommended.
A stencil of 75 μm gives an aspect ratio of 0.77
With a stencil of 100 μm one will obtain an aspect ratio of 0.58
Fig 2. Reflow soldering footprint DFN2510A-10 (SOT1176-1)
sot1176-1_fr
PUSB3AB4
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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