PDF AK2400 Data sheet ( Hoja de datos )

Número de pieza	AK2400
Descripción	High integrated receiver
Fabricantes	AKM
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No Preview Available ! [AK2400] AK2400 High integrated receiver for PMR/LMR Overview □ Operating Supply Voltage : 2.7 to 5.5V □ Wide Operating Temperature Range : -40 to +85C □ Delta-Sigma Fractional-N PLL with a frequency switching function : No glitch operation for AFC(Automatic Frequency Control) and DFM(Digital Frequency Modulation) □ High linearity RF Mixer(1st) and IF Mixer(2nd) □ IF Local frequency selectable as usage : 28.8MHz,45.9MHz,50.4MHz,57.6MHz □ Frequency tripler generates IF Local signal □ Built-in very narrow programmable bandwidth IF BPF (450kHz) □ PLL FM detector □ RSSI function □ Noise squelch circuit □ Built-in 12bits 1Msps SAR ADC □ Audio output signal S/N (Wide/Narrow) : 50dB / 46dB (Typ.) *De-emphasis + BPF □ Compact packaging : 56pin-QFN (8 x 8 mm、0.5 mm pitch) Applications □ Narrowband high performance professional digital wireless systems (Channel spacing for 6.25kHz,12.5kHz) □ Public safety and community wireless systems □ Marine / mobile communication systems □ Low power radio systems □ Monitoring and control telemeter systems 014008989-E-01 1 2015/4 1 page Pin/Function [AK2400] No. Name 1 RFIN 2 AVSS1 3 IFOUTP 4 IFOUTN 5 MIXVDD 6 IFIP 7 AVSS2 8 LO2NDIN 9 TRIOUT 10 REFIN 11 NC 12 NC 13 NC 14 NC 15 AVDD 16 VREFA 17 AGNDOUT 18 AGNDIN 19 BIAS4 20 PDOUT 21 DISCOUT 22 AUDIOOUT 23 NAMPI 24 NAMPO 25 NRECTO 26 RSSIOUT 27 IFOUT 28 ADIN 29 PDN 30 RSTN 31 AD_SDO 32 AD_SCLK 33 AD_CSN 34 CSN Type AI PWR AO AO PWR AI PWR AI AO AI - - - - PWR AO AO AI AO AO AO AO AI AO AO AO AO AI DI DI DO DI DI DI Conditions at power down - - - - - - Function RF signal input pin. Connecting a inductor between this pin and ground. Analog VSS power supply pin IF Output Positive .This pin is open drain output. It needs power feeding via an inductor. IF Output Negative .This pin is open drain output. It needs power feeding via an inductor. Mixer VDD power supply pin IF signal input pin - Analog VSS power supply pin - 2nd LO signal input pin - Tripler circuit output pin - Reference signal input pin Hi-Z This pin must be left open Hi-Z This pin must be left open Hi-Z This pin must be left open Hi-Z This pin must be left open - Analog VDD power supply pin - LDO reference pin. Connect the capacitor to stabilize LDO reference voltage - Analog ground output pin. Connect the capacitor to stabilize the analog ground level. - Analog ground input pin. Connect the capacitor to stabilize the analog ground level. - Output pin to connect bias resistor for reference voltage - Pin1 for Discriminator Low-pass filter - Pin2 for Discriminator Low-pass filter - Demodulated audio signal output pin - Input pin for noise squelch amplifier - Output pin for noise squelch amplifier - Output pin for the rectification circuit - Output pin to connect capacitor for Received Signal Strength Indicator(RSSI) - Output pin for IFBUF - Input pin for A/D converter Hi-Z Power down pin for LDO Hi-Z Hardware reset pin - A/D Converter data output pin for serial data Hi-Z A/D Converter clock input pin for serial data Hi-Z A/D Converter chip select input pin for serial data Hi-Z Chip select input pin for serial data 014008989-E-01 5 2015/4 5 Page [AK2400] ADC AC Timing At first, set {PDADC_N}=”1” to operate the A/D Converter. A/D conversion cycle is started by the falling edge of AD_CSN. AD_SDO outputs “0” synchronized with the falling edge of AD_CSN. AD_SDO outputs “0” until the third falling edge of AD_SCLK. From the fourth falling edge, the results of 12 bits A/D conversion are output with MSB first during the 16th edge. A/D conversion cycle is ended on the 16th falling edge, AD_SDO becomes Hi-Z. After the 16th edge, set AD_CSN =”1”. Since A/D converter becomes acquisition phase after the 16th falling edge of AD_SCLK, AD_CSN pin must keep ”1” during the end of “tq” time after AD_SDO became Hi-Z. It is possible to get the available conversion results from the next cycle, since the first A/D conversion result is the dummy cycle (unavailable result). D11 to D0 : A/D converted data Figure 4 ADC Timing Parameter Symbol Conditions Min. Typ. Max. Unit AD_SCLK frequency fADSCLK 20 MHz Minimum quiet time required between Tq bus relinquish and start of next 40 ns conversion AD_CSN Falling to First SCLK Falling time tCSS 10 ns AD_CSN edge to AD_SDO Tri-State Disabled tDCD 25 ns AD_SCLK Falling to AD_SDO Output Delay time tDOD 15pF load 25 ns AD_SCLK High Pulse Width tCKH 0.4×tA DSCLK ns AD_SCLK Low Pulse Width tCKL 0.4×tA DSCLK ns 16th AD_SCLK Falling to AD_SDO Hi-Z State Delay time tCCZ 25 ns Minimum AD_CSN Pulse Width tCSW 25 ns Note) Digital input and output timing is relative to 0.5DVDD of rising signal and falling signal. 014008989-E-01 11 2015/4 11 Page

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