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PDF MC74VHCT393A Data sheet ( Hoja de datos )
| Número de pieza | MC74VHCT393A | |
| Descripción | Dual 4-Bit Binary Ripple Counter | |
| Fabricantes | ON Semiconductor | |
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MC74VHCT393A
Advance Information
Dual 4−Bit Binary Ripple
Counter
The MC74VHCT393A is an advanced high speed CMOS dual 4−bit
binary ripple counter fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
This device consists of two independent 4−bit binary ripple counters
with parallel outputs from each counter stage. A ÷256 counter can be
obtained by cascading the two binary counters.
Internal flip−flops are triggered by high−to−low transitions of the clock
input. Reset for the counters is asynchronous and active−high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the VHC393.
The VHCT inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V because it has full 5
V CMOS level output swings.
The VHCT393A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage. The
output structures also provide protection when VCC = 0 V. These input and
output structures help prevent device destruction caused by supply
voltage—input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output., The inputs
tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V
systems.
• High Speed: fmax = 170MHz (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C
• TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
PIN ASSIGNMENT
CP1 1
RD1 2
1QA 3
1QB 4
1QC 5
1QD 6
GND 7
14 VCC
13
12 RD2
11 2QA
10 2QB
9 2Q
8 2CQD
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 1
1
http://onsemi.com
MARKING DIAGRAMS
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
14 8
VHCT393A
AWLYWW
17
14 8
VHCT
393A
AWLYWW
17
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
SOIC EIAJ−14
M SUFFIX
CASE 965
14 8
VHCT393A
ALYW
17
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ORDERING INFORMATION
Device
Package Shipping
MC74VHCT393AD
SOIC−16 55 Units/Rail
MC74VHCT393ADR2 SOIC−16 1000 Units/Reel
MC74VHCT393ADT TSSOP−16 96 Units/Rail
MC74VHCT393ADTR2 TSSOP−16 2500 Units/Reel
MC74VHCT393AM
MC74VHCT393AMEL
SOIC
EIAJ−16
SOIC
EIAJ−16
50 Units/Rail
2000 Units/Reel
Publication Order Number:
MC74VHCT393A/D
1 page  
MC74VHCT393A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (Input tr = tf= 3.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Parameter
Maximum
Propagation Delay,
RD to QN
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtOSLH, OutputtoOutput
tOSHL Skew
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCIN MaximumInput
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapacitance
Test Conditions
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
VCC = 3.3 ± 0.3 V
(Note 1)
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 50pF
VCC = 5.0 ± 0.5 V CL = 50pF
(Note 1)
TA = 25°C
Min Typ Max
7.9 12.3
10.4 15.8
5.4 8.1
6.9 10.1
1.5
1.0
4 10
TA = ≤ 85°C
Min Max
1.0 14.5
1.0 18.0
1.0 9.5
1.0 11.5
1.5
1.0
10
TA = ≤ 125°C
Min Max
1.0 14.5
1.0 18.0
1.0 9.5
1.0 11.5
1.5
Unit
ns
ns
pF
1.0 pF
10 pF
Typical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note 2)
23 pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current
power consumption; PD =
can be obtained by
CPD VCC2 fin +
the
ICC
equation:
VCC.
ICC(OPR)
=
CPD
VCC
fin
+
ICC.
CPD
is
used
to
determine
the
no−load
dynamic
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
Symbol
VOLP
VOLV
VIHD
VILD
Parameter
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
TA = 25°C
Typ Max
0.5 0.8
− 0.5
− 0.8
2.0
0.8
Unit
V
V
V
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol
tw
tw
trec
tr, tf
Parameter
Minimum Pulse Width, CP
Minimum Pulse Width, RD
Minimum Recovery Time, RD to CP
Minimum Input Rise and Fall Times
Test Conditions
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
TA = 25°C
Typ Limit
5.0
5.0
5.0
5.0
5.0
4.0
330
100
TA = ≤ 85°C
Limit
5.0
5.0
5.0
5.0
5.0
4.0
330
100
TA = ≤ 125°C
Limit
5.0
5.0
5.0
5.0
5.0
4.0
330
100
Unit
ns
ns
ns
ns
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