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PDF AS1851A Data sheet ( Hoja de datos )
| Número de pieza | AS1851A | |
| Descripción | Digital Power PoE PD Controllers w/HV Isolation & Synchronous DC-DC Converter | |
| Fabricantes | Akros Silicon | |
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AS1851A/31A — Digital Power PoE PD Controllers w/HV Isolation &
Synchronous DC-DC Converter
GENERAL DESCRIPTION
The AS1851A and AS1831A devices each integrate Akros
GreenEdge™ High Voltage Isolation technology with Power-over-
Ethernet (PoE) PD and Synchronous DC-DC power conversion
technology.
The AS1851A includes a 13W/25W (Type 1 and Type 2)
IEEE®802.3af/at compliant PD integrated with high-voltage isolation
and a digital power Synchronous DC-DC converter.
The AS1831A includes a 13W (Type 1) IEEE®802.3af/at compliant
PD integrated with high-voltage isolation and a digital power
Synchronous DC-DC converter.
In addition to enabling digital PoE power conversion, Akros
GreenEdge™ isolation enables direct digital management of both
isolated Primary power and Secondary system power for real time
end-to-end Green Power application capabilities.
TYPICAL APPLICATIONS
Voice-over-IP (VoIP) phones
Wireless LAN & WiMAX access points (WAP)
Pan, Tilt, Zoom (PTZ) Cameras, IP cameras
Thin-client and notebook computers
Fiber-to-the-home (FTTH) terminals
Point-of-sale (PoS) terminals, RFID readers
ORDERING INFORMATION
The AS1851A and AS1831A pin-compatible devices are available in
64-lead QFN Reduction of Hazardous Substance (RoHS) compliant
packages.
Part #
Type 1 Type 2 Hardware
PD PD
Mode
AS1851A*
x
x
x
AS1831A*
x
x
* Industrial Temperature Range, -40°C to 85°C
Software
Mode
x
x
Pwr In
(W)
13/30
13
SIMPLIFIED APPLICATION DIAGRAM
FEATURES
Digitally Isolated Programmable Power
PoE PD Controller
Type 1 and Type 2 IEEE® 802.3af & 802.3at Compliant PD
(AS1851A), Type 1 only (AS1831A)
Automatic PoE-Plus (Type 2) detection in HW and I2C Modes
(AS1851A only)
Low Resistance PD Power FET Switch (0.5 typical)
Primary‐Side DC‐DC Controller
High-efficiency DC-DC Controller with Digital Optimization
Primary-Secondary High-voltage integrated Digital Isolation
Programmable Primary Clock Frequency Local-power operation
Down to 9.5V
Secondary‐Side Sync Power Output
Synchronous Controller with programmable power-FET timing
for high efficiency at both light and full load
Programmable PWM Frequencies synched to External Clock
Power Management
Hardware programmable start-up power sequencing
Primary-side power monitoring & control from Secondary-side
Individual output Power-Good management
Voltage margining for each output
Primary GPIO/ADC controlled via Secondary GPIO or I2C
5V µC-compatible with interrupt on alarm services
Programmable watchdog timer
EMC Compliance and Protection
Slew-rate-controlled power drivers
External PWM sync clock option
Optional spread-spectrum clocking, SW controlled
Over-current, Under/Over-voltage and Short-circuit Protection
High-temperature warning and shutdown
Meets IEC 61000-4-2/3/4/5/6, IEC60747, IEC 60950, DIN
EN60747-5-2 (VDE0884), & UL1577 requirements for EMC
compliance and basic isolation to 2120 VDC (1500 VRMS)
100V Process for PoE transient voltage robustness
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
408.746.9000 http://www.AkrosSilicon.com
1 page  
AS1851A/31A
PIN ASSIGNMENTS AND DESCRIPTIONS
Figure 1 - AS1851A/31A Pin Assignments
Table 1 - AS1851A/31A Signal Descriptions - Primary Side
Pin Name
I/O1 Description
Primary-Side: PD Controller
15 48VIN
P AS1851A/31A startup power input.
Paddle 48RTN
P Input power return. One of three bottom side device connections, 48RTN (Paddle #1) is
#1 connected to the internal PD Power MOSFET source. 48RTN is connected to 48N (Paddle
#2) via this internal inrush current limiting power MOSFET.
Paddle 48N
P Primary-side Transformer power return. One of three bottom side device connections, 48N
#2 (Paddle #2) provides the power return for the DC-DC controller transformer primary. 48N is
connected to the internal PD Power MOSFET drain. 48N is connected to 48RTN via this
internal inrush current limiting power MOSFET.
16 LDET
D, I Local Power Enable Input. Enables use of local power for the DC-DC controller and disables
PD functions. When activated this disables the PoE PD signature capability that normally
uses the RSIG signature resistor.
Refer to Figure 3 for a typical LDET circuit configuration and Table 14 for resistor values. If
Local power detection is not required, connect LDET to 48VIN. Note that LDET must NOT be
tied to 48RTN.
In Software mode, the LDET status can be read from the PD Status & Control Register.
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
408.746.9000 http://www.AkrosSilicon.com
5
5 Page 
AS1851A/31A
RADCIN
ADCERROR
ILADCIN
CADCIN
ADCIN resolution
ADCIN total unadjusted error
ADCIN input leakage current
ADCIN input capacitance
8
±TBD3
1002
0.32
bits Referenced to 48RTN.
LSB Referenced to 48RTN.
nA Referenced to 48RTN.
pF Referenced to 48RTN.
1 Typical values at: Ta = 25°C, Vin = 48VDC. Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation
methods.
2 Guaranteed by design. Not tested in production.
3 Includes offset, full-scale, and linearity.
Table 7 - Primary Side DC-DC Controller Electrical Characteristics
Symbol
Parameter
Min Typ1 Max
VIN_AF
Type 1 PD input voltage
37 48 57
VIN_AT
Type 2 PD input voltage
42.5 48
57
VAUX
Input Voltage, Local Power Mode 9.5
57
VLDET_ON Local input voltage threshold for 48VIN
Local Power Mode - ON
-2.4V
VLDET_OFF Local input voltage threshold for
48VIN
VBIAS
Local Power Mode - OFF
External bias source voltage
82
-1.2V
142
FPWM1L
Low end of Primary PWM
104
switching frequency range
FPWM1H
High end of Primary PWM
512
switching frequency range
FOSC1
PWM1 clock frequency accuracy -20
+20
FPWM1T
PWM switching frequency
0.12
temperature coefficient
RH_GATE GATE drive impedance
6
RL_GATE
VPK1P
DMAX1
DMIN1
GATE drive impedance
Peak current sense threshold
voltage at ISENSEP
Primary PWM Maximum duty
cycle
Primary PWM Minimum duty
cycle
6
395
803
103
Unit
V
V
V
V
V
V
KHz
KHz
%
%/C°
Ω
Ω
mV
%
%
Conditions
Measured at the Network Interface
Measured at the Network Interface
Measured at 48VIN (referenced to 48N)
over full VLDET range
See Table 3 for Absolute Maximum
Rating for LDET (referenced to 48VIN).
Sets VOH of GATE.
Set by external resistors on PRI_DIV
and SEC_DIV pins see Table 15.
Set by external resistors on PRI_DIV
and SEC_DIV pins see Table 15.
See Table 15 for frequency.
Refer to Table 15 for PWM Frequency.
High side output drive resistance,
Source.
Low side output drive resistance, Sink.
Ipeak = VPK1P / RISENSEP.
1 Typical values at: Ta = 25°C, Vin = 48VDC. Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation
methods.
2 Guaranteed by characterization. Not tested in production.
3 Guaranteed by design. Not tested in production.
Table 8 - Secondary Side Sync Controller (Output) Electrical Characteristics
Symbol
Parameter
Min Typ1 Max
Unit
VSYNC_OUT SYNC_OUT voltage
4.5 5
6
V
RH_SYNC
SYNC_OUT
2.5 Ω
Source Impedance
VDD_SYNC = 5V
RL_SYNC
SYNC_OUT
2.5 Ω
Source Impedance
VDD_SYNC = 5V
VMR
Output voltage margining range
±5
%
VREF
ILEA
FB voltage reference
Error amp leakage
0.98 1.0 1.02
12
V
µA
Gm
Feedback Transconductance
150 225 350
µS
(Siemens)
Conditions
Source
Sink
Software mode, see Table 35.
1 Typical values at: Ta = 25°C, Vin = 48VDC. Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation
methods.
2 Guaranteed by design. Not tested in production.
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
408.746.9000 http://www.AkrosSilicon.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS1851A.PDF ] | |
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