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PDF LV8824QA Data sheet ( Hoja de datos )
| Número de pieza | LV8824QA | |
| Descripción | PWM Driver IC | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA2083
LV8824QA
Bi-CMOS IC
For Brushless Motor Drive
PWM Driver IC
http://onsemi.com
Overview
The LV8824QA is a PWM pre-driver IC suitable for use in 3-phase brushless motors. This IC was designed based on
the assumption that Nch FETs are used as the upper and lower output transistors. The rotational speed is controllable by
inputting PWM pulse or DC voltage externally and changing duty. LV8824QA incorporates latch-type constraint
protection circuit.
Features
• IO max = 50mA
• Speed control and synchronous rectification by PWM direct input (3.3V input-ready) and DC voltage.
• 3-Hall FG output
• Latch type constraint protection circuit (latch is released by S/B and F/R.)
• Forward/reverse switch circuit, Hall bias pin
• Power saving circuit
• Current limiter circuit, Low-voltage protection circuit, Thermal shut-down circuit
• Charge pump circuit (external Nch/Nch), 5V regulator output.
• Start/Brake circuit
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
Output current
Allowable power dissipation
VCC max
VG max
IO max
Pd max
VCC pin
VG pin
Mounted on a circuit board.*1
34
42
50
1.45
V
V
mA
W
Junction temperature
Tj max
150 °C
Operating temperature
Topr
-40 to +105 °C
Storage temperature
Tstg
-55 to +150 °C
*1 : Specified circuit board : 100mm × 100mm × 1.6mm, glass epoxy (double-layer board)
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
70412 SY 20120626-S00007 No.A2083-1/13
1 page  
LV8824QA
Three-phase HALL logic truth table (IN = “High” means the following state: IN+ > IN-.)
("Upper gate = VH" and "lower gate = UL" mean the following state: the upper FET connected
F/R = High
IN1 IN2 IN3
to VH pin is on and the lower FET connected to UL pin operates by PWM signal.)
F/R = Low
Driving output
IN1 IN2 IN3
Upper gate
Lower gate (PWM)
HLHLHL
VH
UL
HL L LHH
WH
UL
HHL L LH
WH
VL
LHLHLH
UH
VL
LHHHL L
UH
WL
L LHHHL
VH
WL
3FG output
IN1 IN2 IN3 3FG
HLHL
HL LH
HHL L
LHLH
L HH L
L LHH
S/B pin, PWMIN pin
Input state
High or Open
Low
S/B pin
Stop (short brake)
Start
PWMIN pin
Output OFF
Output ON
Internal Equivalent Circuit and Sample External Component Circuit
CTL input PWMIN input S/B input
PWM
CTL
PWMIN S/B VREG
VCC
F/R input
VREG
F/R
STIME
PWM
F/R
SYNC TIME
A/D (2bit)
CSD
CSD
OSC
CTL
PWMIN
Start/
Brake
5VREG
CHARGE
PUMP
VG
CP2
CP1
LVSD
UH
UOUT
UL
3FG output 3FG
MOSC
LDA
3FG
CONTROL
LOGIC
PRE
DRIVER
VREG
MODE
FG
MODE
SELECT
A/D(2bit)
HALL HYS AMP
HB
GND
IN1+ IN1- IN2+ IN2- IN3+ IN3-
HB
CURR
LIM
VCC
VH
VOUT
VL
WH
WOUT
WL
RF
+ VM
GND
No.A2083-5/13
5 Page 
LV8824QA
9. Hall Input Signal
The amplitude of Hall input should be higher than the hysteresis width (35mV max).
The amplitude should be 100mVp-p or higher to take the influence of noise and phase gap into consideration. If output
wave form is distorted by noise when switching from one phase to another, make sure to insert capacitor between hall
inputs. In constraint protection circuit, Hall input is used as judgment signal. Although the circuit ignores noise to a
certain level, caution is still required. If all 3 phases of Hall input signal turn to the same input state (HHH or LLL), all
of the outputs are turned off. If you use Hall IC, by fixing one input side (either + or -) to the voltage within the range of
common-mode input (0.3V to VREG-1.7V), the other input side accepts input from 0V to VREG.
Connection of Hall elements
Connection (1) (where three Hall elements in serial connection)
Merit
• Compared to parallel connection, current consumption is less
because serial connection enables sharing current among 3 Hall
elements.
• Current limiter resistance is reducible.
• Amplitude variation caused by temperature is less.
Demerit
• Amplitude may not be sufficient because each Hall element is
powered with 1V only.
• Current may fluctuate depends on temperature.
• HALL amplitude tends to be affected by the fluctuation of Hall
elements (especially for input resistor).
Connection (2) (three Hall elements in parallel connection)
Merit
• The current for Hall elements is adjustable with current limiter
resistance.
• Amplitude is sufficient because supply voltage to Hall elements is
adjustable.
Demerit
• Current consumption is large because each Hall element requires
current independently.
• Requires resistor for current limiter.
• Amplitude may fluctuate depends on temperature.
(1)
VCC
HB
3V Constant-voltage Output
(2)
VCC
HB
3V Constant-voltage Output
10. MODE pin
MODE pin allows selecting functions of the IC.
MODE pin sets 4 functions based on input voltage.
MODE pin input voltage
z 0V to 1.0V
z 1.5V to 2.25V
z 2.8V to 3.5V
z 4.2V to (VREG)V
mode
→ mode B & power saving mode
→ mode B & FG output mode
→ mode A & FG output mode
→ mode A & power saving mode
When Duty cycle = 0% is detected
When frequency of PWM input is low
(approx. 7.5kHz or lower)
When the Duty cycle of PWM input is low
(ex. Frequency: 20kHz,
Duty cycle: 3% or lower)
Reverse current detection function
mode A (suitable for fan)
Synchronous rectifier OFF (free operation)
Synchronous rectifier OFF
Synchronous rectifier OFF
Yes (during detection, synchronous rectifier is
OFF)
mode B (suitable for office equipments)
Short brake
Synchronous rectifier ON
Synchronous rectifier ON
No
Power saving mode: When S/B pin = Brake, power saving mode is set. When Duty = 0% is detected as well as when
constraint protection circuit is in operation, HB pin output is turned OFF.
(See “12. HB pin” and “13. Power saving circuit” for further details.)
DG output is always feasible since FG output mode: Power saving mode and HB pin output OFF are not set.
No.A2083-11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet LV8824QA.PDF ] | |
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