PDF HMC832A Data sheet ( Hoja de datos )

Número de pieza	HMC832A
Descripción	25 MHz to 3000 MHz Fractional-N PLL
Fabricantes	Analog Devices
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Data Sheet 25 MHz to 3000 MHz Fractional-N PLL with Integrated VCO HMC832A FEATURES RF bandwidth: 25 MHz to 3000 MHz 3.3 V supply Maximum phase detector rate: 100 MHz Ultralow phase noise −110 dBc/Hz in band (typical), fO at 1600 MHz Fractional figure of merit (FOM): −226 dBc/Hz 24-bit step size, 3 Hz typical resolution Exact frequency mode with 0 Hz frequency error Fast frequency hopping 40-lead, 6 mm × 6 mm LFCSP package: 36 mm2 APPLICATIONS Cellular infrastructure Microwave radios WiMax, WiFi Communications test equipment CATV equipment DDS replacement Military Tunable reference sources for spurious-free performance GENERAL DESCRIPTION The HMC832A is a 3.3 V, high performance, wideband, frac- tional-N, phase-locked loop (PLL) that features an integrated voltage controlled oscillator (VCO) with a fundamental frequency of 1500 MHz to 3000 MHz and an integrated VCO output divider (divide by 1, 2, 4, 6, … 62) that enables the HMC832A to generate continuous frequencies from 25 MHz to 3000 MHz. The integrated phase detector (PD) and Σ-Δ modulator, capable of operating at up to 100 MHz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance. Industry leading phase noise and spurious performance, across all frequencies, enable the HMC832A to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. A low noise floor (−160 dBc/Hz eliminates any contribution to modulator/mixer noise floor in transmitter applications. FUNCTIONAL BLOCK DIAGRAM LD/SDO SCK SDI HMC832A LOCK DETECT CONTROL MODULATOR CAL SPI PROGRAMMING INTERFACE EN EN ÷1, 2, 4, 6, ...62 SEN RF_P RF_N ÷N CP CP PFD ÷R VCO VTUNE XREFP Figure 1. The HMC832A is footprint compatible to the HMC830 PLL with an integrated VCO. It features 3.3 V supply and innovative programmable performance technology that enables the HMC832A to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for improved noise floor performance. Additional features of the HMC832A include 12 dB of RF output gain control in 1 dB steps; an output mute function to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; programmable differential or single-ended outputs, with the ability to select either output in single-ended mode; a Σ-Δ modulator exact frequency mode that enables users to generate output frequencies with 0 Hz frequency error; and a register configurable 3.3 V or 1.8 V serial port interface (SPI). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet Parameter VCO OPEN-LOOP PHASE NOISE fO at 2 GHz13 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset fO at 2 GHz/2 = 1 GHz13 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset fO at 3 GHz/30 = 100 MHz13 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset 250 kHz Offset fO13 fO = 1584 MHz fO = 1998 MHz fO = 2416 MHz fO = 2812 MHz PLL Phase Noise at 20 kHz Offset, 50 MHZ PFD Rate fO = 1582.896 MHz fO = 1998.25 MHz fO = 2415.735 MHz fO = 2811.21 MHz Lock Time Frequency Resolution Fundamental Mode Divider Mode Reference Spurs FIGURE OF MERIT (FOM) Floor Integer Mode Floor Fractional Mode Flicker (Both Modes) Test Conditions/Comments Min Typ HMC832A Max Unit Over manufacturing process variations with 3.3 V power supply at 25°C Over process with 3.3 V power supply at 25°C, measured with >200 kHz loop bandwidth Depends on loop filter bandwidth, PFD rate, and definition of lock (to within ±Hz or ±degrees of settling) Depends on PFD rate and VCO output divider setting 1.5 GHz to 3 GHz output; at typical phase detector frequency (fPD) of 50 MHz, typical resolution = 3 Hz <1.5 GHz output, resolution depends on VCO output divider setting Normalized to 1 Hz (see Figure 24) −88 −116 −139 −157 −162 −93 −122 −145 −159 −162 −110 −139 −160 −163 −163 −124.5 −122.5 −122.0 −121.0 −113.5 −113.5 −112.5 −109.5 500 fPD/224 fPD/(224 × output divider) −85 −229 −226 −268 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz µs Hz Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. B \| Page 5 of 48 5 Page Data Sheet –120 –130 –140 –150 100MHz OUTPUT 55.55MHz OUTPUT –160 25MHz OUTPUT –170 100 1k 10k 100k 1M 10M 100M OFFSET (Hz) Figure 15. Low Frequency Performance, 100 MHz XTAL, PD Frequency = 50 MHz, Loop Filter Type 3 (See Table 13), Integer Mode, 50 MHz Low-Pass Filter at the Output of HMC832A for the 25 MHz Curve Only, Charge Pump Set to Maximum Value –60 –80 –100 –120 –140 –160 –180 1k 10k 100k 1M 10M 100M OFFSET (Hz) Figure 16. Typical Spurious Emissions at 2000.1 MHz, Tunable 47.5 MHz Reference, Loop Filter Type 2 (see Table 13 and the Loop Filter and Frequency Changes Section) –40 HIGH PERFORMANCE MODE ON (VCO_REG 0x03[1:0] = 3d) –60 –80 –100 –120 –140 –160 2854MHz 2453MHz 2013MHz 1587MHz –180 1k 10k 100k 1M 10M OFFSET (Hz) Figure 17. Open-Loop Phase Noise 100M HMC832A –60 –80 –100 –120 –140 –160 –180 1k 10k 100k 1M 10M 100M OFFSET (Hz) Figure 18. Typical Spurious Emissions at 2000.1 MHz, 50 MHz Fixed Reference, 50 MHz PD Frequency, Integer Boundary Spur Inside the Loop Filter Bandwidth (See the Loop Filter and Frequency Changes Section) –60 TYPICAL SPURIOUS vs. OFFSET FROM 2GHz, FIXED REFERENCE = 50MHz –70 –80 –90 –100 TYPICAL SPURIOUS vs. OFFSET FROM 2GHz, TUNABLE REFERENCE ~47.5MHz –110 –120 2000.01 2000.1 2001 OUTPUT FREQUENCY (kHz) Figure 19. Typical Spurious vs. Offset from 2 GHz, Fixed 50 MHz Reference vs. Tunable 47.5 MHz Reference (See the Loop Filter and Frequency Changes Section) –100 –110 –120 –130 100kHz OFFSET ALL MODES 1MHz OFFSET ALL MODES 100MHz OFFSET LOW CURRENT MODE 100MHz OFFSET HIGH PERFORMANCE MODE –40°C +27°C +85°C –140 –150 –160 –170 30 100 300 1000 3000 FREQUENCY (MHz) Figure 20. Open-Loop Phase Noise vs. Frequency at Various Temperatures Rev. B \| Page 11 of 48 11 Page

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