PDF AN32058A Data sheet ( Hoja de datos )

Número de pieza	AN32058A
Descripción	7 x 7 Dots Matrix LED Driver LSI
Fabricantes	Panasonic
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No Preview Available ! DReovcisNioon. . T3A4-EA-04725 Product Standards AN32058A http://www.semicon.panasonic.co.jp/en/ 7 x 7 Dots Matrix LED Driver LSI FEATURES  7 x 7 LED Matrix Driver (Total LED that can be driven = 49)  Built-in memory (ROM and RAM)  LDO : 2-ch  SPI Interface : 1-ch  Driver for RGB color unit : 1-ch  44 pin Plastic Quad Flat Non-leaded package (QFN Type) TYPICAL APPLICATION LED DESCRIPTION AN32058A is 49 Dots Matrix LED Driver. It can drive up to 16 RGB LEDs. APPLICATIONS  Mobile Phone  Smart Phone  PCs  Game Consoles  Home Appliances etc. Battery CPU I/F LDOCNT LEDCTL INT CE CLK DI DO RSTB Y0~Y6 7 X0~X6 7 Note) The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of the above illustrated application circuit in the design of the equipment. Established : 2007-05-24 Revised : 2013-04-15 Page 1 of 64 1 page DReovcisNioon. . T3A4-EA-04725 Product Standards AN32058A ELECTRICAL CHARACTERISTICS VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Current consumption Current consumption (1) Current consumption (2) Current consumption (3) Reference voltage Output voltage Reference current ICC1 ICC2 ICC3 At OFF mode LDOCNT = Low At Standby mode LDOCNT = Low LDO2 is active. LDOCNT = High LDO1 and LDO2 are active. VREF IVREF = 0 A Output voltage Voltage regulator (LDO1) Output voltage Short circuit protection current Ripple rejection (1) Ripple rejection (2) VIREF IIREF = 0 A VL1 IPT1 PSL11 PSL12 ILDO1 = – 30 mA LDOCNT = High REG18 = High VLDO1 = 0 V, IPT1 = ILDO1 VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO1 = – 15 mA PSL11 = 20log (acVLDO1 / 0.2) VB = 3.6 V + 0.2 V[p-p] f = 10 kHz ILDO1 = – 15 mA PSL12 = 20log (acVLDO1 / 0.2) Min Limits Typ Max Unit Note — 0 1 A — — 8 12 A — — 18 24 A — 1.21 1.24 1.27 V — 0.44 0.54 0.64 V — 1.79 1.85 1.91 V — 50 100 200 mA — — – 45 – 40 dB — — – 35 – 25 dB — Established : 2007-05-24 Revised : 2013-04-15 Page 5 of 64 5 Page DReovcisNioon. . T3A4-EA-04725 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note Voltage regulator (LDO1) Output capacitor 1 F, Output capacitor’s ESR less than 0.1  Rise time Tsu1 Time until output voltage reaches to 0 V to 90% — 0.25 — ms 2 3 Fall time Tsd1 Time until output voltage reaches to 10% — 5 — ms 2 3 Maximum load current IOMAX1 — — 15 — mA 3 Load transient response (1) Vtr11 ILDO1 = – 50 A  – 15 mA (1 s) — 70 Load transient response (2) Vtr12 ILDO1 = – 15 mA  – 50 A (1 s) — 70 Voltage regulator (LDO2) Output capacitor 1 F, Output capacitor’s ESR less than 0.1  — mV 3 — mV 3 Rise time Tsu2 Time until output voltage reaches to 0 V to 90% — 0.25 — ms 2 3 Fall time Tsd2 Time until output voltage reaches to 10% — 5 — ms 2 3 Maximum load current IOMAX2 — — 15 — mA 3 Load transient response (1) Vtr21 ILDO2 = – 50 A  – 15 mA (1 s) — 70 — mV 3 Load transient response (2) Vtr22 ILDO2 = – 15 mA  – 50 A (1 s) — 70 — mV 3 TSD (Thermal shutdown circuit) Detection temperature Tdet Temperature which LDO1, LDO2, Constant current circuit, Matrix SW and RGB turns off. — 160 — C 3 4 Return temperature Tsd11 Returning temperature — 110 — C 3 5 Note) 2 : Rise time and Fall time are defined as below. Actual evaluation result of rise time : LDO1 : 290 to 400 s, LDO2 : 220 to 310 s Actual evaluation result of fall time : LDO1 : 6.2 to 8.5 ms, LDO2 : 5.8 to 7.9 ms 3 : Typical Design Value 4 : LDO1, LDO2, Constant current circuit, and Matrix SW and RGB are turned off when TSD is High. When TSD is High, the register is set as 14hD1 = 1. However, data can be read only when the register is read immediately after INT occurs since internal regulator is turned off. 5 : Only LDO1 and LDO2 return after ON state of TSD. A logic part will be in Reset state. LDOCNT Serial LDO1 90% Tsu1 LDO2 90% Tsu2 Established : 2007-05-24 Revised : 2013-04-15 10% 10% Tsd1 Tsd2 Page 11 of 64 11 Page

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