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PDF STM32F102C4 Data sheet ( Hoja de datos )
| Número de pieza | STM32F102C4 | |
| Descripción | 32-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STM32F102x4
STM32F102x6
Low-density USB access line, ARM®-based 32-bit MCU with
16/32 KB Flash, USB FS, 5 timers, ADC & 5 com. interfaces
Datasheet - production data
Features
• Core: ARM® 32-bit Cortex®-M3 CPU
– 48 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 WS memory access
– Single-cycle multiplication and hardware
division
• Memories
– 16 or 32 Kbytes of Flash memory
– 4 or 6 Kbytes of SRAM
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• Debug mode
– Serial wire debug (SWD) and JTAG
interfaces
• DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
• 1 × 12-bit, 1.2 µs A/D converter (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
• Up to 51 fast I/O ports
– 37/51 I/Os all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant
LQFP64
10 × 10 mm
LQFP48
7 × 7 mm
• Up to 5 timers
– Two 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 2 watchdog timers (Independent and
Window)
– SysTick timer: 24-bit downcounter
• Up to 5 communication interfaces
– One I2C interface (SMBus/PMBus)
– Two USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– One SPI (12 Mbit/s)
– One USB 2.0 full speed interface
• CRC calculation unit, 96-bit unique ID
• ECOPACK® packages
Table 1. Device summary
Reference
Part number
STM32F102x4 STM32F102C4, STM32F102R4
STM32F102x6 STM32F102C6, STM32F102R6
May 2015
This is information on a product in full production.
DocID15057 Rev 5
1/78
www.st.com
1 page  
STM32F102x4, STM32F102x6
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DocID15057 Rev 5
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5
5 Page 
Description
STM32F102x4, STM32F102x6
/3#?/54
/3#?).
/3#?).
/3#?/54
-#/
Figure 2. Clock tree
4O &LASH PROG IF &,)4&#,+
-(Z
(3) 2#
(3)
0,,32# 0,,-5,
X
X X X
0,,
53"
0RESCALER
-(Z
53"#,+
TO 53" INTERFACE
-(Z MAX
(#,+
TO !(" BUS CORE
#LOCK
MEMORY AND $-!
37
%NABLE BITS
TO #ORTEX 3YSTEM TIMER
&#,+ #ORTEX
(3)
0,,#,+
(3%
393#,+ !("
-(Z
MAX
0RESCALER
!0"
0RESCALER
FREE RUNNING CLOCK
-(Z MAX
0#,+
TO !0"
0ERIPHERAL #LOCK PERIPHERALS
%NABLE BITS
#33
4)- 4)-
TO 4)- 4)-
)F !0" PRESCALER X
4)-8#,+
ELSE X 0ERIPHERAL #LOCK
%NABLE BITS
-(Z
(3% /3#
0,,8402%
!0"
0RESCALER
-(Z MAX
0#,+
TO !0"
0ERIPHERAL #LOCK PERIPHERALS
%NABLE BITS
,3% /3#
K(Z
,3%
TO 24#
24##,+
!$#
0RESCALER
TO !$#
!$##,+
24#3%,;=
,3) 2#
K(Z
,3) TO )NDEPENDENT 7ATCHDOG )7$'
)7$'#,+
-AIN
#LOCK /UTPUT
-#/
0,,#,+
(3)
(3%
393#,+
,EGEND
(3% HIGH
SPEED EXTERNAL CLOCK SIGNAL
(3) HIGH
SPEED INTERNAL CLOCK SIGNAL
,3) LOW
SPEED INTERNAL CLOCK SIGNAL
,3% LOW
SPEED EXTERNAL CLOCK SIGNAL
AIB
1. For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output
(USBCLK) at 48 MHz.
2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.
3. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.
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| PDF Descargar | [ Datasheet STM32F102C4.PDF ] | |
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