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PDF NTAG203 Data sheet ( Hoja de datos )
| Número de pieza | NTAG203 | |
| Descripción | NFC Forum Type 2 Tag compliant IC | |
| Fabricantes | NXP Semiconductors | |
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NTAG203
NFC Forum Type 2 Tag compliant IC with 144 bytes user
memory
Rev. 3.0 — 17 October 2011
213830
Product data sheet
COMPANY PROPRIETARY
1. General description
NXP Semiconductors has developed NTAG203 - NFC Forum Type 2 Tag compliant IC - to
be used with NFC enabled devices according to NFC Forum technical specifications (see
Ref. 10 and Ref. 11), according to NFC Forum recommendations or Proximity Coupling
Devices (PCD), according to ISO/IEC 14443A (see Ref. 1). The communication layer (RF
Interface) complies to parts 2 and 3 of the ISO/IEC 14443A standard. The NTAG203 is
primarily designed for NFC Forum Type 2 Tag applications (i.e. Smart Advertisement,
connection handover, Bluetooth simple pairing, WiFi Protected set-up, call request, SMS,
goods and device authentication and others).
1.1 Contactless energy and data transfer
Communication to NTAG can be established only when the IC is connected to a coil. Form
and specification of the coil is out of scope of this document.
When the NTAG is positioned in the RF field, the high speed RF communication interface
allows the transmission of the data with a baud rate of 106 kbit/s.
NTAG IC
NFC TAG
ENERGY
DATA
NFC
ENABLED DEVICE
Fig 1. NFC Tag interacting with NFC enabled device
001aao403
1 page  
NXP Semiconductors
NTAG203
NFC Forum Type 2 Tag compliant IC with 144 bytes user memory
7. Mechanical specification
Table 4.
Wafer
diameter
Wafer specifications
thickness
flatness
Potential Good Dies per Wafer (PGDW)
Sawing method
Wafer backside
material
treatment
roughness
Chip dimensions
chip size
scribe lines
Passivation
type
material
thickness
Au bump
material
hardness
shear strength
height
height uniformity
within a die
within a wafer
wafer to wafer
flatness
size
LA, LB
TP1, TP2, VSS
size variation
under bump metallization
Remark: Substrate is connected to VSS.
8” wafer, 200 mm unsawn
min: 200 mm
typ: 206 mm
max: 210 mm
120 m 15 m
not applicable
61942
laser dicing
Si
ground and stress relieve
Ra max 0.2 m
Rt max 2 m
0.673 mm 0.673 mm
x-line:15 m 5 m
y-line:15 m 5 m
sandwich structure
Nitride
1.75 m
> 99.9 % pure Au
35 – 80 HV 0.005
> 70 MPa
18 m
2 m
3 m
4 m
1.5 m
60 m 60 m
60 m 60 m
5 m
sputtered TiW
NTAG203
Product data sheet
COMPANY PROPRIETARY
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 17 October 2011
213830
© NXP B.V. 2011. All rights reserved.
5 of 30
5 Page 
NXP Semiconductors
NTAG203
NFC Forum Type 2 Tag compliant IC with 144 bytes user memory
8.5.2 Lock bytes
Lock bytes enable the user to lock parts of the complete memory area for writing. A Read
from user memory area cannot be restricted via lock bytes functionality.
The lock bytes functionality is enabled with a WRITE command (see Section 8.8.7
“WRITE”) or COMPATIBILITY WRITE command (see Section 8.8.8 “COMPATIBILITY
WRITE”), where 2 out of 4 bytes transmitted are used for setting the lock bytes. Two
corresponding bytes - either bytes 2 and 3 for page 02h or bytes 0 and 1 for page 28h -
and the actual content of the lock bytes are bit-wise “OR-ed”. The result of OR operation
becomes the new content of the lock bytes. Two unused bytes do not have to be
considered. Although included in the COMPATIBILITY WRITE or WRITE command, they
are ignored when programming the memory.
Table 6. Lock bytes
Name
Number
Lock byte 0
2
Lock byte 1
2
Lock byte 2
40
Lock byte 3
40
Page
Address
02h
02h
28h
28h
Function
page and block locking
page locking
page and block locking
functionality and block locking
Due to the built-in bitwise OR operation, this process is irreversible. If a bit is set to “1”, it
cannot be changed back to “0” again. Therefore, before locking the lock bytes, the user
must ensure that the corresponding user memory area and/or configuration bytes are
correctly written.
The configuration written in the lock bytes is active upon the next REQA or WUPA
command.
The single bits of the 4 bytes available for locking incorporate 3 different functions:
• the read-only locking of the single pages or blocks of the user memory area
• the read-only locking of the single bytes of the configuration memory area
• the locking of the lock bits themselves
For the compatibility reasons, the first 64 bytes (512 bits) of the memory area have the
same functionality as MIFARE Ultralight (MF0ICU1, see also Ref. 7), meaning that the two
lock bytes used for the configuration of this memory area are identically configured. The
mapping of single bits to memory area for the first 64 bytes (512 bits) is shown in Figure 6.
The bits of byte 2 and 3 of page 02h represent the field-programmable read-only locking
mechanism. Each page x from 03h (OTP bits) to 0Fh may be locked individually to
prevent further write access by setting the corresponding locking bit Lx to 1. After locking
the page is read-only memory.
The 3 least significant bits of lock byte 0 of page 2 are the block-locking bits. Bit 2 handles
pages 0Fh to 0Ah, bit 1 pages 09h to 04h and bit 0 page 03h (OTP bits). Once the block
locking bits are set, the locking configuration for the corresponding memory area is frozen.
NTAG203
Product data sheet
COMPANY PROPRIETARY
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 17 October 2011
213830
© NXP B.V. 2011. All rights reserved.
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