PDF IS42S16160 Data sheet ( Hoja de datos )

Número de pieza	IS42S16160
Descripción	16Meg x16 256-MBIT SYNCHRONOUS DRAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS42S16160 16Meg x16 256-MBIT SYNCHRONOUS DRAM SEPTEMBER 2009 FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S16160 Vdd Vddq 3.3V 3.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 8K refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Available in Industrial Temperature • Available in 54-pin TSOP-II and 54-ball TF-BGA • Available in Lead-free OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. IS42S16160 4M x16x4 Banks 54-pin TSOPII 54-ball TF-BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 6 7 10 10 166 143 100 100 5.4 5.4 8 8 -75E Unit – ns 7.5 ns – Mhz 133 Mhz – ns 5.5 ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 09/15/09 1 1 page IS42S16160 PIN FUNCTIONS Symbol Type A0-A12 Input Pin BA0, BA1 CAS CKE CLK CS DQML, DQMH Input Pin Input Pin Input Pin Input Pin Input Pin Input Pin DQ0-DQ15 Input/Output RAS Input Pin WE Vddq Vdd Vssq Vss Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin Function (In Detail) Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-A12) and READ/WRITE command (column address A0-A8 (x16); with A10 defin- ing auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands. The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQML and DQMH control the lower and upper bytes of the I/O buffers. In read mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to OE in conventional DRAMs. In write mode,DQML and DQMH control the input buffer. When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot be written to the device. Data on the Data Bus is latched on DQ pins during Write commands, and buffered for output after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the "Com- mand Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Com- mand Truth Table" item for details on device commands. Vddq is the output buffer power supply. Vdd is the device internal power supply. Vssq is the output buffer ground. Vss is the device internal ground. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 09/15/09 5 5 Page IS42S16160 FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Address Write Recovering H × × × × L H H H × L H H L × L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L H × L L L L OC, BA Write Recovering H × × × × with Auto L H H H × Precharge L H H L × L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L H × L L L L OC, BA Refresh H × × × × L H H × × L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L H × L L L L OC, BA Mode Register H × × × × Accessing L H H H × L H H L × L H L × BA, CA, A10 L L × × BA, RA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/WRITE ACT/PRE/PALL REF/MRS Action Nop, Enter row active after tDPL Nop, Enter row active after tDPL Nop, Enter row active after tDPL Begin read (8) Begin new write ILLEGAL (3) ILLEGAL (3) ILLEGAL ILLEGAL Nop, Enter precharge after tDPL Nop, Enter precharge after tDPL Nop, Enter row active after tDPL ILLEGAL(3,8,11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL ILLEGAL Nop, Enter idle after tRC Nop, Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop, Enter idle after 2 clocks Nop, Enter idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don’t satisfy tDPL. 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, but legal for other banks. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 09/15/09 11 11 Page

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