PDF SST49LF160C Data sheet ( Hoja de datos )

Número de pieza	SST49LF160C
Descripción	16 Mbit LPC Flash
Fabricantes	Silicon Storage Technology
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No Preview Available ! 16 Mbit LPC Flash SST49LF160C FEATURES: 160C16Mb LPC Flash Advance Information • Organized as 2M x8 • Conforms to LPC Interface Specification – Support Single-Byte LPC Memory Read/Write Cycles • Single 3.0-3.6V Read and Write Operations • LPC Mode – 5-signal LPC bus interface for both in-system and factory programming using programmer equipment – 33 MHz clock frequency operation – WP#/AAI and TBL# pins provide hardware Write protect for entire chip and/or top Boot Block – Block Locking Registers for individual block Read- Lock, Write-Lock, and Lock-Down protection – 5 GPI pins for system design flexibility – 4 ID pins for multi-chip selection – Status register for End-of-Write detection – Program-/Erase-Suspend Read or Write to other blocks during Program-/Erase-Suspend • Two-cycle Command Set • Security ID Feature – 256-bit Secure ID space - 64-bit Unique Factory Pre-programmed Device Identifier - 192-bit User-Programmable OTP • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Read Current: 12 mA (typical) – Standby Current: 10 µA (typical) • Uniform 4 KByte sectors – 35 Overlay Blocks: one 16-KByte Boot Block, two 8-KByte Parameter Blocks, one 32-Kbyte Parameter Block, thirty-one 64-KByte Main Blocks. • Fast Sector-Erase/Program Operation – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Program Time: 7 µs (typical) • Auto Address Increment (AAI) for Rapid Factory Programming (High Voltage Enabled) – RY/BY# pin for End-of-Write detection – Multi-Byte Program – Chip Rewrite Time: 4 seconds (typical) • Packages Available – 32-lead PLCC • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST49LF160C flash memory device is designed to interface with host controllers (chipsets) that support a low- pin-count (LPC) interface for system firmware applications. The SST49LF160C device complies with the LPC Interface Specification. The LPC interface operates with 5 signal pins versus 32 pins of a 8-bit parallel flash memory. This frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall system costs due to simpli- fied signal routing. The SST49LF160C uses a 5-signal LPC interface to sup- port both in-system and rapid factory programming using programmer equipment. A high voltage pin (WP#/AAI) is used to enable Auto Address Increment (AAI) mode. The SST49LF160C offers hardware block protection in addition to individual block protection via software registers for critical system code and data. A 256-bit Security ID space with a 64-bit factory pre-programmed unique number and a 192- bit user programmable OTP area enhances the user’s abil- ity to use new security techniques and implement a new data protection scheme. The SST49LF160C also provides general purpose inputs (GPI) for system design flexibility. The SST49LF160C flash memory device is manufactured with SST’s proprietary, high-performance SuperFlash tech- nology. The split-gate cell design and thick-oxide tunneling injector attain greater reliability and manufacturability com- pared with alternative technology approaches. The SST49LF160C device significantly improves performance and reliability, while lowering power consumption. The SST49LF160C device writes (Program or Erase) in-system with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. ©2006 Silicon Storage Technology, Inc. S71315-00-000 4/06 1 The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation. These specifications are subject to change without notice. 1 page 16 Mbit LPC Flash SST49LF160C LIST OF TABLES Advance Information TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TABLE 2: Transfer Size Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3: LPC Memory Cycles START Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 4: LPC Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 5: LPC Memory Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 6: Boot Device Physical Addresses Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 7: LPC Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 8: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 9: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 10: Software Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 11: Security ID Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 12: General Purpose Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 13: Block Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 14: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TABLE 15: Security ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TABLE 16: JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 17: LPC Memory Map Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 18: LD# Input and RY/BY# Status in AAI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 19: AAI Programming Cycle (initiated with WP#/AAI at VH ONLY) . . . . . . . . . . . . . . . . . . . . . . . . 25 TABLE 20: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 21: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 22: Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 23: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 24: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 25: Reset Timing Parameters, VDD=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TABLE 26: Read/Write Cycle Timing Parameters, VDD=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . 30 TABLE 27: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 28: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 29: Input Cycle Timing Parameters, VDD=3.0-3.6V (AAI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TABLE 30: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ©2006 Silicon Storage Technology, Inc. 5 S71315-00-000 4/06 5 Page 16 Mbit LPC Flash SST49LF160C Load Enable The Load Enable pin (LD#), is an input pin which when low, indicates the host is loading data in an AAI programming cycle. Data is loaded in the SST49LF160C at the rising edge of the clock. If LD# is high, it signals the AAI interface that the host is terminating the command. LD# low/high switches the RY/BY# output from buffer free flag to pro- gramming complete flag (see Table 18). No Connection (NC) These pins are not connected internally. DESIGN CONSIDERATIONS SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket. The RST# pin must remain stable at VIH for the entire dura- tion of an Erase operation. WP#/AAI must remain stable at VIH for the entire duration of the Erase and Program opera- tions for non-Boot Block sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at VIH for the entire duration of the Erase and Program operations. MODE SELECTION The SST49LF160C flash memory device operates in two distinct interface modes: the LPC mode and the Auto Address Increment (AAI) mode. The WP#/AAI pin is used to set the interface mode selection. The device is in AAI mode when the WP#/AAI pin is set to the Supervoltage VH (9±0.5V), and in the LPC mode when the WP#/AAI is set to VIL/VIH. The mode selection must be configured prior to device operation. LPC MODE Advance Information Device Operation The SST49LF160C supports Single-Byte LPC Memory Read and Write cycle types as defined in Low Pin Count Interface Specification. Table 2 shows the size of transfer supported by the SST49LF160C. TABLE 2: Transfer Size Supported Cycle Type LPC Memory Read LPC Memory Write Size of Transfer 1 Byte 1 Byte T2.0 1315 The LPC mode uses a 5-signal communication interface: one control line, LFRAME#, which is driven by the host to start or abort a bus cycle, a 4-bit data bus, LAD[3:0], used to communicate cycle type, cycle direction, ID selection, address, data and sync fields. The device enters standby mode when LFRAME# is taken high and no internal opera- tion is in progress. The host drives LFRAME# signal from low-to-high to cap- ture the start field of a LPC cycle. On the cycle in which LFRAME# goes inactive, the last latched value is taken as the START value. The START value determines whether the SST49LF160C will respond to a LPC Memory Read/ Write cycle type as defined in Table 3. TABLE 3: LPC Memory Cycles START Field Definition START Value Definition 0000 Start of an LPC memory cycle. The direction (Read or Write) is determined by the second field of the LPC cycle. T3.1 1315 See following sections on details of LPC Memory cycle types (Tables 4 and 5). Two-cycle Program and Erase command sequences are used to initiate LPC Memory Program and Erase operations. See Table 8 for a listing of Program and Erase commands. ©2006 Silicon Storage Technology, Inc. 11 S71315-00-000 4/06 11 Page

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