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PDF MTC1207A Data sheet ( Hoja de datos )
| Número de pieza | MTC1207A | |
| Descripción | 10 Gb/s 16-Bit MUX/CMU | |
| Fabricantes | Multilink | |
| Logotipo |  |
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10 Gb/s
16-Bit MUX/CMU
MIXED SIGNAL INTEGRATED CIRCUIT PRODUCTS
MTC1207A, MTC1207B
Product Data Sheet
Applications
• Telecom transmission systems
• SONET OC-192 and SDH STM-64 equipment
• Forward Error Correction data rates supported
(10.664 Gb/s option)
Features
• 16 to 1 multiplexer (MUX)
• Reduced power consumption (2.5 W)
• Large output data amplitude
• Integrated Clock Multiplier Unit (CMU)
• Low Jitter VCO with external loop filter
• Jitter performance complies with SONET/SDH standards
Description
The MTC1207A and 1207B are reduced power 10 Gb/s 16 to 1 multiplexers (MUX) with an
integrated clock multiplier unit for use in SONET OC-192, SDH STM-64, and Forward Error
Correction (FEC) systems. The MTC1207A accepts 16 different data channels at 622 Mb/s and
combines them into a single 9.953 Gb/s serial data stream suitable for transmission over high speed
fiberoptic networks. The MTC1207B accepts differential data at 666.5 Mb/s and is optimized for use
in systems which employ FEC encoding at 10.664 Gb/s.
For each of the two devices, the minimum data output amplitude is 800 mVpp, allowing direct
connection to an external modulator driver such as the MTC5515. An on-chip Phase/Frequency
Detector (PFD) and precision Voltage Controlled Oscillator (VCO) are used in combination with an
external op-amp loop filter to convert the 622 or 666.5 MHz reference clock, supplied by the host
system, into a low jitter 9.953 or 10.664 GHz clock output. The 10 Gb/s data output is retimed with
respect to the high speed clock using an internal D flip flop (DFF).
All data and clock I/O are provided with on-chip 50 Ohm transmission line terminations to minimize
the external component count. The MTC1207 series devices are provided in a 128 pin quad flat
pack (QFP) and operate from -5.0 V and -3.5 V power supplies. The circuitry was designed for use
in equipment which is required to comply with Bellcore, ANSI, and ITU-T international standards for
SONET and SDH systems.
Data
Processor
D0
D15
REFCLK
Figure 1: Typical System Block Diagram
Modulator
Driver
(MTC5515)
10 Gb/s
Serial
Data
MTC1207A,
MTC1207B
Light
Source
External
Modulator
Fiberoptic
Link
Photo
Receiver
10 Gb/s
Serial
Data
CDR
DMUX
(MTC1224)
D0
D15
C16
Page 1
Data
Processor
1 page  
10 Gb/s
16-Bit MUX/CMU
MIXED SIGNAL INTEGRATED CIRCUIT PRODUCTS
MTC1207A, MTC1207B
Product Data Sheet
CLK160
D0
D1
D15
SEL1
SEL2
16:1
RG MULTIPLEXER
C/16 C/8 C/4 C/2
Phase
Select
Asynchronous
Counter
DFF
OUT
OUT/
CLK
Tx
VCO
VCO
CLK160
REFCLK
Phase/
Frequency
Detector
Figure 2: Block Diagram
tCLK160
ts th
UP
DO
D0-D15
D0-D15
D0-D15
REFCLK
OUT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
CLK
tCLK
Figure 3: Timing Diagram
Page 5
5 Page 
10 Gb/s
16-Bit MUX/CMU
MIXED SIGNAL INTEGRATED CIRCUIT PRODUCTS
MTC1207A, MTC1207B
Product Data Sheet
Pin Name
99 DN
100 UP
101 GND
102 REFCLK/
103 GND
104 REFCLK
105 GND
106 CLK16O/
107 GND
108 CLK16O
109 GND
110 NC
111 GND
112 D0/
113 GND
114 D0
115 GND
116 D1/
117 GND
118 D1
119 GND
120 D2/
121 GND
122 D2
123 GND
Description
Phase frequency detector down, negative going pulses. Connect to external PLL loop
(refer to evaluation circuit schematic).
Phase frequency detector up, negative going pulses. Connect to external PLL loop
(refer to evaluation circuit schematic).
Ground
Function
input, output,
control, supply,
no connect
control
control
supply
Reference clock input (inverting). Connect to 622 MHz (MTC1207A) or 666.5 MHz
(MTC1207B) reference clock. On-chip 50 Ω termination to ground provided. (note:
155.52/166.625 MHz available using PFDSEL pin 94)
Ground
input
supply
Reference clock input (non-inverting). Connect to 622 MHz (MTC1207A) or 666.5 MHz
(MTC1207B) reference clock. On-chip 50 Ω termination to ground provided. (note:
155.52/166.625 MHz available using PFDSEL pin 94)
Ground
input
supply
622 MHz (MTC1207A) or 666.5 MHz (MTC1207B) clock output (inverting). Clock
divided by 16. Back terminated 50 Ω to ground.
Ground
output
supply
622 MHz (MTC1207A) or 666.5 MHz (MTC1207B) clock output (non-inverting). Clock
divided by 16. Back terminated 50 Ω to ground.
Ground
output
supply
No connection.
NC
Ground
supply
Data bit 0 input - 622 Mb/s (MTC1207A) or 666.5 Mb/s (MTC1207B) (inverting). On-chip
50 Ω termination to ground provided.
Ground
input
supply
Data bit 0 input - 622 Mb/s (MTC1207A) or 666.5 Mb/s (MTC1207B) (non-inverting). On-
chip 50 Ω termination to ground provided.
Ground
input
supply
Data bit 1 input - 622 Mb/s (MTC1207A) or 666.5 Mb/s (MTC1207B) (inverting). On-chip
50 Ω termination to ground provided.
Ground
input
supply
Data bit 1 input - 622 Mb/s (MTC1207A) or 666.5 Mb/s (MTC1207B) (non-inverting). On-
chip 50 Ω termination to ground provided.
Ground
input
supply
Data bit 2 input - 622 Mb/s (MTC1207A) or 666.5 Mb/s (MTC1207B) (inverting). On-chip
50 Ω termination to ground provided.
Ground
input
supply
Data bit 2 input - 622 Mb/s (MTC1207A) or 666.5 Mb/s (MTC1207B) (non-inverting). On-
chip 50 Ω termination to ground provided.
Ground
input
supply
Page 11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MTC1207A.PDF ] | |
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