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PDF ESD8104 Data sheet ( Hoja de datos )
| Número de pieza | ESD8104 | |
| Descripción | ESD Protection Diode | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ESD8104 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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ESD8104
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8104 is designed to protect high speed data lines from
ESD. Ultra−low capacitance and low ESD clamping voltage make this
device an ideal solution for protecting voltage sensitive high speed
data lines. The flow−through style package allows for easy PCB layout
and matched trace lengths necessary to maintain consistent impedance
between high speed differential lines such as USB 3.0/3.1 and HDMI
2.0.
Features
• Low Capacitance (0.37 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• USB 3.0/3.1
• eSATA
• HDMI 1.3/1.4/2.0
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15 kV
±15 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
www.onsemi.com
UDFN10
CASE 517BB
MARKING
DIAGRAM
4C MG
G
4C = Specific Device Code (tbd)
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
N/C N/C GND N/C N/C
10 9 8 7 6
12 3 4 5
I/O I/O GND I/O I/O
I/O I/O I/O I/O
Pin 1 Pin 2 Pin 4 Pin 5
Pins 3, 8
Note: Common GND − Only Minimum of 1 GND connection required
=
ORDERING INFORMATION
Device
Package Shipping
ESD8104MUTAG
UDFN10
3000 /
(Pb−Free) Tape & Reel
SZESD8104MUTAG UDFN10
3000 /
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 6
1
Publication Order Number:
ESD8104/D
1 page  
ESD8104
Without ESD8104
With ESD8104
Figure 9. USB 3.0 Eye Diagram with and without ESD8104. 5 Gb/s
Without ESD8104
With ESD8104
Figure 10. HDMI 2.0 Eye Diagram with and without ESD8104. 6 Gb/s
Without ESD8104
With ESD8104
Figure 11. USB 3.1 Eye Diagram with and without ESD8104. 10 Gb/s
See application note AND9075/D for further description of eye diagram testing methodology.
www.onsemi.com
5
5 Page 
ESD8104
ESD Protection Device Technology
ON Semiconductor’s portfolio contains three main
technologies for low capacitance ESD protection device
which are highlighted below and in Figure 17.
• ESD7000 series: Zener diode based technology. This
technology has a higher breakdown voltage (VBR)
limiting it to protecting chipsets with larger geometries.
• ESD8000 series: Silicon controlled rectifier (SCR) type
technology. The key advatange for this technology is a
low holding voltage (VH) which produces a deeper
snapback that results in lower voltage over high
currents as shown in the TLP results in Figure 18. This
technology provides optimized protection for chipsets
with small geometries against thermal failures resulting
in chipset damage (also known as “hard failures”).
• ESD8100 series: Low voltage punch through (LVPT)
type technology. The key advatange for this technology
is a very low turn-on voltage as shown in Figure 19.
This technology provides optimized protection for
chipsets with small geometries against recoverable
failures due to voltage peaks (also known as “soft
failures”).
Figure 17. ON Semiconductor’s Low-cap ESD Technology Portfolio
20 10
18
16 8
14
12 6
10
84
6 ESD8004
ESD8104
4
ESD7004
2
2
00
0 2 4 6 8 10 12 14 16 18 20
VC (V)
Figure 18. High Current, TLP, IV Characteristic of Each Technology
www.onsemi.com
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ESD8104.PDF ] | |
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