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PDF ESD8351 Data sheet ( Hoja de datos )
| Número de pieza | ESD8351 | |
| Descripción | ESD Protection Diode | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ESD8351, SZESD8351
ESD Protection Diodes
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD8351 Series ESD protection diodes are designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.
Features
• Low Capacitance (0.55 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
ISO 10605
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• USB 2.0
• eSATA
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ISO 10605 330 pF / 2 kW Contact
ESD
ESD
ESD
±15 kV
±15 kV
±30 kV
Maximum Peak Pulse Current
8/20 ms @ TA = 25°C
Ipp 5.0 A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
www.onsemi.com
X3DFN2
CASE 152AF
MARKING
DIAGRAMS
PIN 1
M
2
1
SOD−323
CASE 477
AE
M
2
1
SOD−523
CASE 502
AF
12
SOD−923
CASE 514AB
AC M
X, XX = Specific Device Code
M = Date Code
PIN CONFIGURATION
AND SCHEMATIC
1
Cathode
2
Anode
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 6
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
ESD8351/D
1 page  
ESD8351, SZESD8351
IEC 61000−4−2 Spec.
Level
First Peak
Test Volt- Current Current at
age (kV)
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at
60 ns (A)
2
4
6
8
IEC61000−4−2 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 8. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
ESD Gun
TVS
Oscilloscope
50 W
Cable
50 W
Figure 9. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
www.onsemi.com
5
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| PDF Descargar | [ Datasheet ESD8351.PDF ] | |
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