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PDF NCP4206 Data sheet ( Hoja de datos )
| Número de pieza | NCP4206 | |
| Descripción | VR11.1 Digital Programmable Multi-Phase Synchronous Buck Converter | |
| Fabricantes | ON Semiconductor | |
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NCP4206
VR11.1 Digital
Programmable Multi-Phase
Synchronous Buck
Converter with SMBus
The NCP4206 is an integrated power control IC with a SMBus
interface. The NCP4206 is a highly efficient, multiphase, synchronous
buck switching regulator controller, which aids design of High
Efficiency and High Density solutions. The NCP4206 can be
programmed for 1−, 2−, 3−, 4−, 5− or 6 phase operation, allowing for
the construction of up to 6 complementary buck switching stages.
The NCP4206 supports PSI, which is a power state indicator and
can be used to reduce the number of operating phases at light loads.
The SMBus interface enables digital programming of key system
parameters to optimize system performance and provide feedback to
the system.
The NCP4206 has a built in shunt regulator that allows the part to be
powered from the +12 V system supply through a series resistor. The
NCP4206 is specified over the extended commercial temperature
range of 0°C to +85°C and is available in a 48 Lead QFN package.
Features
• Selectable 1−, 2−, 3−, 4−, 5− or 6 Phase Operation at Up to 1.5 MHz
per Phase
• Logic−level PWM Outputs for Interface to External High Power
Drivers
• Fast−Enhanced PWM Flex Mode for Excellent Load Transient
Performance
• Active Current Balancing Between All Output Phases
• Built−in Power−good/Crowbar Blanking Supports On−the−Fly VID
Code Changes
• Digitally Programmable 0.375 V to 1.6 V Output Supports VR11.1
Specifications
• Short−Circuit Protection With Latch−off Delay
• Supports PSI# − Power Saving Mode During Light Loads
• This is a Pb−Free Device
Typical Applications
• Desktop PC
• Servers
http://onsemi.com
1 48
QFN 48
CASE 485AJ
MARKING DIAGRAM
NCP4206
AWLYYWWG
A = Assembly Lot
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
PIN ASSIGNMENT
VCC3
PWRDG
ALERT
SDA
SCL
EN
GND
NC
NC
IMON
IREF
RT
1
2
3
4
5
6
7
8
9
10
11
12
PIN 1
INDICATOR
NCP4206
TOP VIEW
(Not to Scale)
36 PWM3
35 PWM4
34 PWM5
33 PWM6
32 VCC
31 VCC
30 SW1
29 SW2
28 SW3
27 SW4
26 SW5
25 SW6
© Semiconductor Components Industries, LLC, 2013
September, 2013 − Rev. 2
ORDERING INFORMATION
Device
NCP4206MNR2G
Package
QFN48
(Pb−Free)
Shipping†
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1 Publication Order Number:
NCP4206/D
1 page  
NCP4206
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage Range (Note 1)
FBRTN
PWM2 to PWM6, Rampadj
SW1 to SW6
Vin
VFBRTN
−0.3 to 6
−0.3 to +0.3 V
−0.3 to Vin + 0.3
−5 to +25 V
V
V
V
V
SW1 to SW6 (< 200 ns)
−10 to +25 V
V
All other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
TSTG
−0.3 to Vin + 0.3
−65 to 150
0 to 85
V
°C
°C
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
ESDHBM
ESDMM
TSLD
1.5
150
260
kV
V
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: v150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, QFN, 7 x 7 mm (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Symbol
RθJA
Value
27
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
Unit
°C/W
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN − GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 6 and 8)
Parameter
Test Conditions
Symbol Min Typ Max Unit
REFERENCE CURRENT
Reference Bias Voltage
Reference Bias Current
ERROR AMPLIFIER
RIREF = 121 kW
VIREF
IIREF
1.75 1.8 1.85 V
15 mA
Output Voltage Range
Accuracy
Load Line Positioning Accuracy
VCOMP
0
4.4 V
Relative to nominal DAC output, referenced
to FBRTN (Note 8)
VFB
−9.0
+9.0 mV
In startup
VFB(BOOT) 1.091 1.1 1.109 V
−77 −80 −83 mV
Load Line Range
−350
0 mV
Load Line Attenuation
0 100 %
Differential Non−linearity
−1.0 +1.0 LSB
Input Bias Current
IFB = IIREF
IFB 13.3 15 18.5 mA
6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area.
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
8. Refer to Application Information Note.
9. Values based on design and/or characterization.
http://onsemi.com
5
5 Page 
NCP4206
voltage to the programmed VID DAC voltage (either higher
or lower) using 6.25 mV steps.
The soft start slew rate is programmed using Bits <2:0> of
the Ton_Rise (0xD5) command code. Table 4 provides the
soft start values. Figure 8 shows typical start−up waveforms
for the NCP4206.
Table 4. SOFT−START CODES
Code
000
001
010
011
100
101
110
111
Soft−Start (V/msec)
0.3
0.3
0.5 = default
0.7
0.9
1.1
1.3
1.5
Figure 8. Typical Start−up Waveforms
Channel 1: CSREF
Channel 2: EN
Channel 3: PWM1
Phase Detection
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the NCP4206
operates as a 6−phase PWM controller.
To operate as a 5−phase controller connect PWM6 to VCC.
To operate as a 4−phase controller, connect PWM5and
PWM6 to VCC. To operate as a 3−phase controller, connect
PWM4, PWM5 and PWM6 to VCC. To operate as a 2−phase
controller connect PWM3, PWM4, PWM5 and PWM6, to
VCC. To operate as a 1−phase controller connect PWM2,
PWM3, PWM4, PWM5 and PWM6 to VCC.
Prior to soft start, while EN is low, the PWM6, PWM5,
PWM4, PWM3 and PWM2 pins sink approximately 100 mA
each. An internal comparator checks each pin’s voltage
versus a threshold of 3 V. If the pin is tied to VCC, it is above
the threshold. Otherwise, an internal current sink pulls the
pin to GND, which is below the threshold. PWM1 is low
during the phase detection interval that occurs during the
first eight clock cycles of TD2. After this time, if the
remaining PWM outputs are not pulled to VCC, the 100 mA
current sink is removed, and they function as normal PWM
outputs. If they are pulled to VCC, the 100 mA current source
is removed, and the outputs are put into a high impedance
state.
The PWM outputs are logic−level devices intended for
driving fast response external gate drivers such as the
ADP3121. Because each phase is monitored independently,
operation approaching 100% duty cycle is possible. In
addition, more than one output can be on at the same time to
allow overlapping phases.
Master Clock Frequency
The clock frequency of the NCP4206 is set with an
external resistor connected from the RT pin to ground. The
frequency follows the graph in Figure 3. To determine the
frequency per phase, the clock is divided by the number of
phases in use. If all phases are in use, divide by 6. If 4 phases
are in use divide by 4.
Output Voltage Differential Sensing
The NCP4206 combines differential sensing with a high
accuracy VID DAC and reference, and a low offset error
amplifier. This maintains a worst−case specification of
±10 mV differential sensing error over its full operating
output voltage and temperature range. The output voltage is
sensed between the FB pin and FBRTN pin. FB is connected
through a resistor, RB, to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN is
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 70 mA to allow
accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
Output Current Sensing
The NCP4206 provides a dedicated current−sense
amplifier (CSA) to monitor the total output current for
proper voltage positioning versus load current, for the
IMON output and for current−limit detection. Sensing the
load current at the output gives the total real time current
being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low−side
MOSFET. This amplifier can be configured several ways,
depending on the objectives of the system, as follows:
• Output inductor DCR sensing without a thermistor for
lowest cost.
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11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NCP4206.PDF ] | |
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