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PDF SH69P20C Data sheet ( Hoja de datos )
| Número de pieza | SH69P20C | |
| Descripción | OTP 1K 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH69P20C
OTP 1K 4-bit Micro-controller
Features
SH6610C-based single-chip 4-bit micro-controller
OTP ROM: 1K X 16 bits
RAM: 96 X 4 bits
- 32 System control register
- 64 Data memory
Operation voltage:
- fOSC = 30kHz - 4MHz, VDD = 2.4V - 5.5V
- fOSC = 30kHz - 8MHz, VDD = 4.5V - 5.5V
15 CMOS bi-directional I/O pins and 1 CMOS input pin
4-Level Stack (Including Interrupts)
One 8-bit auto re-loaded Timer/Counter
Warm-up Timer
Powerful interrupt sources:
- External0 interrupt: PORTA0
- Internal interrupt (Timer0)
- External1 interrupt: PORTA3
- External Interrupts: PORTB & PORTC (Rising/Falling
Edge)
Oscillator: (Code Option)
- Crystal oscillator:
32.768kHz, 400kHz - 8MHz
- Ceramic resonator: 400kHz - 8MHz
- External RC oscillator: 400kHz - 8MHz
- Internal RC oscillator: 2MHz/4MHz/6MHz
- External clock:
30kHz - 8MHz
Instruction Cycle Time (4/fOSC)
Two Low Power Operation Modes: HALT And STOP
Reset
- Built-in Watchdog Timer (WDT) (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) (Code Option)
Internal reliable reset circuit
Two-level low voltage reset (LVR) (Code Option)
Chip form, DIP, SOP Package
General Description
SH69P20C is a single-chip 4-bit micro-controller. This device integrates a SH6610C CPU core, RAM, ROM, Timer, I/O
ports and 2MHz/4MHz/6MHz internal RC. The SH69P20C is suitable for home appliance application.
Pin Configuration
PORTA.2
PORTA.3
T0/PORTD.2
RESET/PORTD.3
GND
PORTB.0
PORTB.1
PORTB.2
PORTB.3
1
2
3
4
5
6
7
8
9
18 PORTA.1
17 PORTA.0
16 OSCI/PORTD.1
15 OSCO/PORTD.0
14 VDD
13 PORTC.3
12 PORTC.2
11 PORTC.1
10 PORTC.0
1 V2.5
1 page  
SH69P20C
2.2. Configuration of System Register (continued)
Address
$0A
$0B
$0C - $0D
Bit3
PC.3
PD.3
-
Bit2
PC.2
PD.2
-
Bit1
PC.1
PD.1
-
Bit0
PC.0
PD.0
-
R/W Remarks
R/W PORTC data register
R/W PORTD data register
- Reserved
$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table Branch Register
$0F INX.3 INX.2 INX.1 INX.0 R/W Pseudo index register
$10 DPL.3 DPL.2 DPL.1 DPL.0 R/W Data pointer for INX low nibble register
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble register
$12
$13 - $14
$15
$16
$17
-
-
-
PACR.3
PBCR.3
DPH.2
-
PDCR.2
PACR.2
PBCR.2
DPH.1
-
PDCR.1
PACR.1
PBCR.1
DPH.0
-
PDCR.0
PACR.0
PBCR.0
R/W Data pointer for INX high nibble register
- Reserved
R/W PORTD input/output control register
R/W PORTA input/output control register
R/W PORTB input/output control register
$18 PCCR.3
$19 PULLEN
$1A - $1B
$1C
$1D
$1E
$1F
-
-
-
WDT
-
PCCR.2
PH/PL
-
-
-
WDT.2
-
PCCR.1
PBCFR
-
T0S
-
WDT.1
-
PCCR.0
EINFR
-
T0E
-
WDT.0
-
R/W PORTC input/output control register
Bit0: External interrupt (PA.0/PA.3) rising/falling edge
control register
R/W Bit1: PBC interrupt rising/falling edge control register
Bit2: Port Pull-high/Pull-low control register
Bit3: Port Pull-high/Pull-low enable control register
- Reserved
R/W Bit0: T0 signal edge, Bit1: T0 signal source
- Reserved
R/W Bit2-0: Watchdog timer control register
R Bit3: Watchdog timer overflow flag register (Read only)
- Reserved
3. ROM
The ROM can address 1024 X 16 bits of program area from $000 to $3FF.
3.1. Vector Address Area ($000 to $004)
The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt
service routine such as starting vector address.
Address
$000
$001
$002
$003
$004
Instruction
JMP*
JMP*
JMP*
JMP*
JMP*
Remarks
Jump to RESET service routine
Jump to External 0 interrupt service routine
Jump to TIMER0 interrupt service routine
Jump to External 1 interrupt service routine
Jump to Port interrupt service routine
*JMP instruction can be replaced by any instruction.
5
5 Page 
SH69P20C
System Register $19
Address Bit3
Bit2
$19 PULLEN PH/PL
1X
0X
X1
X0
XX
XX
XX
XX
Bit1
PBCFR
X
X
X
X
1
0
X
X
Bit0
EINFR
X
X
X
X
X
X
1
0
R/W Remarks
Bit0: External interrupt (PA.0/PA.3) rising/falling edge
control register
R/W Bit1: PBC interrupt rising/falling edge control register
Bit2: Port Pull-high/Pull-low control register
Bit3: Port Pull-high/Pull-low enable control register
R/W Port Pull-high/Pull-low enable
R/W Port Pull-high/Pull-low disable
R/W Port Pull-high resistor ON
R/W Port Pull-low resistor ON
R/W PBC Rising Edge interrupt
R/W PBC Falling Edge interrupt
R/W External Rising Edge interrupt
R/W External Falling Edge interrupt
To turn on the pull-high resistor, user must set PULLEN to “1”, set PH/PL to “1”, and write “1” to the port data register.
To turn on the pull-low resistor, user must set PULLEN to “1”, clear PH/PL to “0”, and write “0” to the port data register.
PORTB, PORTC Interrupt
The PORTB and PORTC are used as port interrupt sources. Following is the port interrupt function block-diagram.
IEP
PB.n
PC.n
PBCR.n
PCCR.n
Note: n = 0, 1, 2, 3
Rising/Falling
Edge Detector
PBCFR
Port Interrupt
IRQP
Port Interrupt (PBC INT) PROGRAMMING NOTES
If user wants to generate an interrupt when a rising edge from GND to VDD emerges in the port, the following must be
executed.
1. Set the port as input port, fill port data register with “0” and avoid port floating.
2. Pull-low the port (Use external pull-low resistance or set PULLEN to “1” and clear PH/PL to “0”).
3. Set Rising Edge register. (Set PBCFR to “1” in PBC INT application.)
And further rising edge transition would not be able to make interrupt request until all of the pins return to GND in PBC
INT application.
If user wants to generate an interrupt when a falling edge from VDD to GND emerges on the port, the following must be
executed.
1. Set the port as input port, fill port data register with “1” and avoid port floating.
2. Pull-high the port (Use external pull-high resistance or set PULLEN to “1” and set PH/PL to “1”).
3. Set Falling Edge register. (Clear PBCFR to “0” in PBC INT application.)
And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD in PBC INT
application.
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet SH69P20C.PDF ] | |
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