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PDF SH69K20A Data sheet ( Hoja de datos )
| Número de pieza | SH69K20A | |
| Descripción | 1K 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH69K20A
1K 4-bit Micro-controller
Features
SH6610C-based single-chip 4-bit micro-controller
ROM: 1K X 16 bits
RAM: 96 X 4 bits
- System register: 32 X 4 bits
- Data memory: 64 X 4 bits
Operation voltage:
- fOSC = 400kHz - 4MHz, VDD = 2.0V - 5.5V
- fOSC = 4MHz - 8MHz, VDD = 4.5V - 5.5V
15 CMOS bi-directional I/O pins and 1 CMOS input pin
Built-in pull-high and pull-low resistor for PORTA, B, C,
D (excluding PORTD.3 - no pull-high resistor)
4-level subroutine nesting (including interrupts)
One 8-bit auto re-load timer/counter, can be switched
to external clock source
Powerful interrupt sources:
- Internal interrupt: Timer0
- External 0 interrupt: PORTA.0
- External 1 interrupt: PORTA.3
- PORT's rising/falling edge interrupt: PORTBC
Oscillator: (Code Option)
- Crystal oscillator:
- Ceramic resonator:
32.768kHz, 400kHz - 8MHz
400kHz - 8MHz
- External RC oscillator: 400kHz - 8MHz
- Internal RC oscillator: 2MHz/4MHz/6MHz
- External clock:
30kHz - 8MHz
Instruction cycle time:
- 4/32.768kHz (≈ 122.1us) for 32.768kHz
- 4/8MHz (= 0.5us) for 8MHz at VDD = 5.0V
Built-in 2MHz/4MHz/6MHz RC Oscillator (Code Option)
Internal reliable reset circuit
Low voltage reset function (LVR) (Code Option)
Warm-up timer for power on reset
Built-in watchdog timer (Code Option)
Two low power operation modes: HALT and STOP
MASK type
18-pin DIP/SOP Package
General Description
SH69K20A is a single-chip micro-controller integrated with SRAM, ROM, Timer and I/O port, with a built-in
2MHz/4MHz/6MHz RC oscillator.
Pin Configuration
PORTA.2
PORTA.3
T0/PORTD.2
RESET/PORTD.3
GND
PORTB.0
PORTB.1
PORTB.2
PORTB.3
1
2
3
4
5
6
7
8
9
18 PORTA.1
17 PORTA.0
16 OSCI/PORTD.1
15 OSCO/PORTD.0
14 VDD
13 PORTC.3
12 PORTC.2
11 PORTC.1
10 PORTC.0
1 V1.0
1 page  
SH69K20A
3. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep
data after the CPU enters STOP or HALT mode.
3.1 RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $01F
Data memory: $020 - $05F
3.2 Configuration of System Register
System Register $00-$1F RAM Map:
Address Bit3 Bit2 Bit1 Bit0 R/W
Remarks
$00
IEX0
IET0
IEX1
IEP R/W Interrupt enable flags
$01 IRQX0 IRQT0 IRQX1 IRQP R/W Interrupt request flags
$02 - TM0.2 TM0.1 TM0.0 R/W Timer0 Mode register (Prescaler)
$03 - - - - - Reserved
$04 TL0.3 TL0.2 TL0.1 TL0.0 R/W Timer0 load/counter register low digit
$05 TH0.3 TH0.2 TH0.1 TH0.0 R/W Timer0 load/counter register high digit
$06 - $07
$08
$09
-
PA.3
PB.3
-
PA.2
PB.2
-
PA.1
PB.1
-
PA.0
PB.0
- Reserved
R/W PORTA
R/W PORTB
$0A
$0B
$0C - $0D
PC.3
PD.3
-
PC.2
PD.2
-
PC.1
PD.1
-
PC.0
PD.0
-
R/W PORTC
R/W PORTD
- Reserved
$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table Branch Register
$0F INX.3 INX.2 INX.1 INX.0 R/W Pseudo index register
$10 DPL.3 DPL.2 DPL.1 DPL.0 R/W Data pointer for INX low nibble
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble
$12 - DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble
$13 - $14
-
-
-
- - Reserved
$15 - PD2OUT PD1OUT PD0OUT R/W PORTD input/output control
$16 PA3OUT PA2OUT PA1OUT PA0OUT R/W PORTA input/output control
$17 PB3OUT PB2OUT PB1OUT PB0OUT R/W PORTB input/output control
$18 PC3OUT PC2OUT PC1OUT PC0OUT R/W PORTC input/output control
$19 PULLEN PH/PL PBCFR EINFR
$1A - $1B
$1C
$1D
$1E
$1F
-
-
-
WD
-
-
-
-
WDT.2
-
T0S
-
WDT.1
-
T0E
-
WDT.0
---
Bit0: External 0/External 1 interrupt
(PORTA.0/PORTA.3) rising/falling edge set
R/W Bit1: PORTBC interrupt rising/falling edge set
Bit2: Port pull-high/pull-low set
Bit3: Port pull-high/pull-low enable control
- Reserved
R/W Bit0: T0 signal edge, Bit1: T0 signal source
- Reserved
R/W Bit2-0: Watchdog timer control
R Bit3: Watchdog timer overflow flag (Read only)
- Reserved
5
5 Page 
SH69K20A
8. Interrupt
Four interrupt sources are available on SH69K20A:
- Timer0 interrupt
- PORTBC interrupts (Rising/Falling edge)
- External 0 interrupt (Rising/Falling edge)
- External 1 interrupt (Rising/Falling edge)
8.1 Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the
program. Those flags are cleared to “0” at initialization by the chip reset.
Address Bit 3
Bit 2
Bit 1
Bit 0
R/W
Remarks
$00
IEX0
IET0
IEX1
IEP R/W
Interrupt enable flags
$01
IRQX0
IRQT0
IRQX1
IRQP
R/W
Interrupt request flags
When IEx is set to “1” and the interrupt request is generated (IRQx is “1”), the interrupt will be activated and vector
address will be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC
and CY flag will be saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all
interrupt enable flags (IEx) are reset to “0” automatically, so when IRQx is “1” and IEx is set to “1” again, the interrupt will
be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Servicing Sequence Diagram:
Interrupt Nesting:
12345
Inst.cycle
Instruction
Execution
N
Instruction
Execution
I1
Instruction
Execution
I2
Interrupt Generated
Interrupt Accepted
Vector Generated
Stacking
Fetch Vector address
Reset IE.X
Start at vector address
During the SH6610C CPU interrupt service, the user can enable any interrupt enable flag before returning from the
interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the
interrupt request is ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the
next two instructions executed. However, if instruction I1 or instruction I2 disables the interrupt request or enables flag,
then the interrupt service will be terminated.
8.2 External Interrupt
External 0 interrupt is shared with the PORTA.0 and External 1 interrupt is shared with PORTA.3, falling/rising edge
active. When the bit3 of the register $00 (IEX0) is set to “1”, the external 0 interrupt is enabled; when the bit1 of the
register $00 (IEX1) is set to “1”, the external1 interrupt is enabled.
If user wants to generate an External Interrupt when a Rising Edge from GND to VDD, the following must be executed:
(1) Set the PORTA.0/PORTA.3 as input port;
(2) Pull-low the port (Use external pull-low resistance or set PULLEN to “1” and clear PH/PL to “0”).
(3) Set Rising Edge register. (Set EINFR to “1”)
And further rising edge transition would not be able to make interrupt request until PORTA.0 / PORTA.3 return to GND.
If user wants to generate an External Interrupt when a Falling Edge from VDD to GND, the following must be executed:
(1) Set the PORTA.0/PORTA.3 as input port;
(2) Pull-high the port (Use external pull-high resistance or set PULLEN to “1” and set PH/PL to “1”).
(3) Set Falling Edge register. (clear EINFR to “0”)
And further falling edge transition would not be able to make interrupt request until PORTA.0 / PORTA.3 return to VDD.
11
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