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PDF SH66P14A Data sheet ( Hoja de datos )
| Número de pieza | SH66P14A | |
| Descripción | OTP 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH66P14A
OTP 4-bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit microcontroller
OTPROM: 4096 X 16 bits
RAM: 512 X 4 bits (System & Data memory)
Operation voltage: 2.4V - 5.5V
8 CMOS bi-directional I/O pins
4-Level subroutine nesting (include interrupts)
One 8-bit auto re-load timer/counter
8-bit Base timer
Powerful interrupt sources:
- External interrupts ( INT0 )
- Internal interrupt (Timer0)
- Internal interrupt (Base Timer)
- Port's falling edge interrupt: PORTB ( INT1 )
LCD driver:
- 240 dots (1/8 duty 1/4 bias)
- 136 dots (1/4 duty 1/3 bias)
LCD used as scan output
Built-in dual tone PSG with one noise generator
2 Clock source
OSC: (code option)
- Crystal oscillator 32.768K
- RC oscillator: 262K
OSCX: (system register select)
- Ceramic oscillator 455K
- RC oscillator 1.8M or 2M
Instruction cycle time:
- 122.07µs for 32.768 KHz crystal
- 15.27µs for 262 KHz RC
- 8.79µs for 455KHz ceramic
- 2.22µs for 1.8 MHz RC
- 2µs for 2.0 MHz RC
Two low power operation mode: HALT and STOP
Low power consumption
Warm up timer for power on reset
General Description
SH66P14A is a single chip microcontroller integrated with SRAM, OTP ROM, Timer and Dual-tone PSG, LCD driver and I/O
port. This chip builds in a dual-oscillator to enhance the total chip performance.
Pad Configuration
S S S S S S S S S S S S S CC
EEEEEEEEEEEEE 87
GGGGGGGGGGGGG / /
1 1 2 2 2 2 2 2 2 2 2 2 3 SS
8 9 0 1 2 3 4 5 6 7 8 9 0 31 32
SEG17 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
SEG16 45
28 COM6/SEG33
SEG15 46
27 COM5/SEG34
SEG14 47
26 COM4
SEG13 48
25 COM3
SEG12 49
24 COM2
SEG11
SEG10
50
51
SH66P14A
23 COM1
22 OSCI
SEG9 52
21 OSCO
SEG8 53
GND 20
PC.0
SEG7 54
19 OSCXO
SEG6 55
18 OSCXI
SEG5 56
SEG4 57
17 PA.0
VDD
9 16 PA.1
58 1 2 3 4 5 6 7 8
10 11 12 13 14 15 PA.2
_
S S S V V V VT RPP P P P P
E E E L 1 2 3 E E C. B. B. B. B. A.
GGGC
321D
S S1 3 21 03
T
E
T
1 V2.1
1 page  
SH66P14A
3. RAM
Built-in SRAM contains general-purpose data memory, LCD RAM, and system registers. They can be directly accessed in one
instruction cycle. Because of its static nature, the RAM can keep data after the CPU enters STOP or HALT.
3.1. Data memory, LCD RAM, and System Register
The following is the memory allocation map:
$000 - $01F: System register and I/O
$020 - $1FF: Data memory (480 X 4bits, divided into 4 banks)
$300 - $321, $328 - $345, $350 - $36D: LCD RAM space (30 X 8 bits or 34 X 4 bits)
3.2. Data Pointer
The Data Pointer can indirectly address data memory. Pointer address is located in register DPM (3-bits) and DPL (4-bits).
The addressing range can have 128 locations. Pseudo index address (INX) is used to read or write Data memory, and then
RAM address bit9-bit0 comes from DPH, DPM and DPL.
3.3. Configuration of System Register
Address Bit3 Bit2 Bit1 Bit0
Function
Initial
Value
R/W
$00
IEX
IET0
IEBT
IEP Interrupt enable flags
0000 R/W
$01 IRQX IRQT0 IRQBT IRQP Interrupt request flags
0000 R/W
$02 TM0.3 TM0.2 TM0.1 TM0.0 Timer0 mode register
0000 R/W
$03 BTM.3 BTM.2 BTM.1 BTM.0 Base timer mode register
0000 R/W
$04 T0L.3 T0L.2 T0L.1 T0L.0 Timer0 load/counter low nibble
0000 R/W
$05 T0H.3 T0H.2 T0H.1 T0H.0 Timer0 load/counter high nibble
0000 R/W
$06 - $07
-
-
-
- Reserved
--
$08
PA.3
PA.2
PA.1
PA.0 PORTA
0000 R/W
$09
PB.3
PB.2
PB.1
PB.0 PORTB
0000 R/W
$0A -
-
PC.1
PC.0 Bonding option
01 (default) R
$0B PACR.3 PACR.2 PACR.1 PACR.0 Set PORTA to be output port
0000
W
$0C PBCR.3 PBCR.2 PBCR.1 PBCR.0 Set PORTB to be output port
LPD Enable Control (LPD3 - 0):
$0D LPD3 LPD2 LPD1 LPD0 0101: LPD Enable (Default);
1010: LPD Disable
$0E TBR.3 TBR.2 TBR.1 TBR.0 Table branch register
0000
W
0101
W
0000 R/W
$0F INX.3 INX.2 INX1 INX.0 Index register (INX)
0000 R/W
$10 DPL3 DPL2 DPL1 DPL0 Data pointer for INX low nibble
0000 R/W
$11 - DPM.2 DPM.1 DPM.0 Data pointer for INX middle nibble
0000 R/W
$12 - DPH.2 DPH.1 DPH.0 Data pointer for INX high nibble
0000 R/W
Bit1, 2: PA.1 & PA.2 as PSG output or I/O PORT
$13 PPULL PAM2 PAM1 HLM Bit0: Heavy load mode
0000 R/W
Bit3: Port pull-up control
Bit0: Turn on OSCX oscillator
$14 OXS - OXM OXON Bit1: CPU clocks select (1: OSCX/0: OSC)
Bit3: OSCX type selection
0000 R/W
5
5 Page 
SH66P14A
PSG subblock diagram
SEL0 SEL1
OSC
OSCX
/2
CLK-SLECTOR
/16
PSG CLK
Figure 3. MPX block diagram
SEL1 SEL0
Clk source
0 0 OSC
OSC = 32.768K
OSC = 262K
0 1 OSC/2 OSC = 32.768K
OSC = 262K
1 0 OSCX
OSCX = 1.8M
OSCX = 455K
1 1 OSCX/16 OSCX = 1.8M
OSCX = 455K
The MPX block selects 4 clock sources as PSG clk that provides for the two channel clk sources.
Channel 1.
CH1EN OCT1
REGISTER
C1.6~C1.0
PSG clk
32.768K
262K
16.384K
131K
1.8M
455K
112.5K
28.4K
OCT1
0
1
Channel 2.
PSG CLK
/8
Scaling ratio
1
1/8
SELECTOR
DIVIDER1
/2 CH1 OUT
Channel 1 is constructed by a 7-bit pseudo random counter.
Channel 1 is enabled/disabled by CH1EN. It creates either a
sound frequency or an alarm carrier frequency or a remote
carrier frequency.
PSG CLK
CH2EN OCT2
/8
SELECTOR
C2.3~C2.0 C1M
NOISE
GENERATOR
C2.14~C2.0
REGISTER
C2.14~C2.0
C2.14~C2.8
DIVIDER2
/2
C2M
SELECTOR
CH2 OUT
OCT2
0
1
1Hz
4Hz
8Hz
32Hz
ENEVLOP
Scaling ratio
1
1/8
ENEVLOP
Channel 2 is constructed by a 15-bit pseudo random
counter. Channel 2 is enabled/disabled by CH2EN
It can be a 15-bit wide-band noise generator or a 7-bit sound
generator. It can also create an alarm envelope signal.
C2M
0
1
x
C1M
0
0
1
CH1 is Sound generator.
CH1 is Sound generator.
CH1 is Sound generator.
Function
CH2 is Sound generator.
CH2 is Noise generator.
CH2 is Alarm mode register.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH66P14A.PDF ] | |
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