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PDF MSC8102ADS Data sheet ( Hoja de datos )
| Número de pieza | MSC8102ADS | |
| Descripción | User Manual | |
| Fabricantes | Motorola Semiconductors | |
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User’s Manual
MSC8102UM/D
Version 1.2
December 17, 2002
MSC8102ADS
User’s Manual
© Motorola, Inc., 2002
1 page  
Table of Contents
4.7.1
4.7.2
SDRAM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.8 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.9
4.9.1
4.9.2
4.9.3
TDM Port Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Time Slot Interchanger (TSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
E1/T1 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.10 RS232 Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.11 Packet Peripherals (Host-side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.11.1 ATM SONET Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.11.2 10/100 T-Base Ethernet Phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.12 Board Control & Status Register - BCSR . . . . . . . . . . . . . . . . . . . 62
4.12.1 BCSR0 - Board Control / Status Register 0. . . . . . . . . . . . . . . . . . 63
4.12.2 BCSR1 - Board Control / Status Register 1. . . . . . . . . . . . . . . . . . 64
4.12.3 BCSR2 - Board Control / Status Register 2. . . . . . . . . . . . . . . . . . 65
4.12.4 BCSR3 - Board Control / Status Register 3. . . . . . . . . . . . . . . . . . 66
4.12.5 BCSR4 - Board Status Register - 4 . . . . . . . . . . . . . . . . . . . . . . . . 67
4.12.6 BCSR5 - Board Identification Register - 5 . . . . . . . . . . . . . . . . . . 68
4.12.7 BCSR6 - Board Miscellaneous Register - 6. . . . . . . . . . . . . . . . . . 69
Section 5 Support Info
5.1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.1 Host 60-x Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.2 Slave System Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Host Memory Controller Registers’ Programming. . . . . . . . . . . . 76
5.3 Slave Memory Controller Registers’ Programming . . . . . . . . . . . 79
5.4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4.1 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
P1,P5 - Stereo Phone Jack Connectors . . . . . . . . . . . . . . . . . . . . . 84
P2 - SMB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Logic Analyzer Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
P6 - RJ45 E1/T1 Line Connector. . . . . . . . . . . . . . . . . . . . . . . . . . 85
P10 - Slave UART Port Connector . . . . . . . . . . . . . . . . . . . . . . . . 85
P13 - Altera’s In System Programming (ISP) . . . . . . . . . . . . . . . . 86
P14 - Host Debug OnCE (SYS) Connector . . . . . . . . . . . . . . . . . 86
MSC8102ADSUM/D Ver. 1.2
User’s Manual
V
5 Page 
Getting Started
Section 1 Getting Started
This Quick Start Guide shows MSC8102ADS board switches and jumpers in their default posi-
tions.
1.1 Switches
ADS Dual-In-Line Package (DIP) Switches are listed and described in Table 1-1. The switches
and jumpers featured in this chapter are shown with their factory-default positions. ADS board
LED’s are also detailed.
Table 1-1 The ADS Switches
Designator & Purpose
Type
Description
SW4.1-SW4.2 set the MODCK1,2 of MSC8102
Slave to the PLL mode. When “ON”, the value is
zero. When there is a clock-in frequency of
41.6MHz, the clock mode is set to 11.
SW4
Slave Configuration Control
(MSC8102)
MODCK2
MODCK1
SYS DSI
DBG
CFG-S Ctrl
SW4.3 (SYS <-> DSI) selects the power-up
configuration source. MSC8101 Host is the
configuration source when the DSI position is
chosen. If SYS is selected then the MSC8102
Slave Flash is the configuration source.
SW4.4 While in DBG position, EE0 input is high at
the time of Core reset. This allows the Cores to
enter Debug mode immediately after negation of
HRESETs. When not in the DBG position then,
after reset, the Cores run freely. The Debug mode
may be activated by toggling SW4/4.
Factory settings:
- MODCK1,2 are OFF
- Config source from DSI
- Debug mode after Slave’s Hard Reset
SW5
Software Option reading by
MSC8101
-0
-1
-2
HEE1
SW Opt
SW5.1-SW5.3 set Software Option Bits 0-2 for SW
flow control. When “ON”, the value is zero.
SW5.4 is used for Host EE1 pin control after
Power-On-Reset. When “ON”, the value is zero.
Reset Factory settings:
- All bits set to ON
MSC8102ADSUM/D Ver. 1.2
User’s Manual
15
11 Page | ||
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| PDF Descargar | [ Datasheet MSC8102ADS.PDF ] | |
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