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PDF ISL6217A Data sheet ( Hoja de datos )
| Número de pieza | ISL6217A | |
| Descripción | Precision Multi-Phase Buck PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
June 30, 2005
ISL6217A
FN9107.3
Precision Multi-Phase Buck PWM
Controller for Intel, Mobile Voltage
Positioning IMVP-IV™ and IMVP-IV+™
The ISL6217A Multi-Phase Buck PWM controller IC, with
integrated half bridge gate drivers, provides a precision
voltage regulation system for advanced Pentium IV
microprocessors in notebook computers. Two-phase
operation eases the thermal management issues and load
demand of Intel’s latest high performance processors. This
control IC also features both input voltage feed-forward and
average current mode control for excellent dynamic
response, “Loss-less” current sensing using MOSFET
rDS(ON) and user-selectable switching frequencies from
250kHz to 1MHz per phase.
The ISL6217A includes a 6-bit digital-to-analog converter
(DAC) that dynamically adjusts the CORE PWM output
voltage from 0.700V to 1.708V in 16mV steps and conforms
to the Intel IMVP-IV™ and IMVP-IV+™ mobile VID
specification. The ISL6217A also has logic inputs to select
Active, Deep Sleep and Deeper Sleep modes of operation. A
precision reference, remote sensing and proprietary
architecture, with integrated, processor-mode, compensated
“Droop”, provide excellent static and dynamic CORE voltage
regulation.
To improve efficiency at light loading, the ISL6217A can be
configured to run in single phase PWM in ACTIVE, DEEP or
DEEPER SLEEP modes of operation. Also, in deep and
deeper sleep modes the ISL6217A will operate in diode
emulation.
Another feature of this IC controller is the PGOOD monitor
circuit that is held low until CORE voltage increases, during
its soft-start sequence, to within 12% of the “Boot” voltage.
This PGOOD signal is masked during VID changes. Output
overcurrent, overvoltage and undervoltage are monitored
and result in the converter latching off and PGOOD signal
being held low.
The overvoltage and undervoltage thresholds are 112% and
84% of the VID, Deep or Deeper Sleep setpoint,
respectively. Overcurrent protection features a 32 cycle
overcurrent shutdown. PGOOD, overvoltage, undervoltage
and overcurrent provide monitoring and protection for the
microprocessor and power system. The ISL6217A IC is
available in a 38 lead TSSOP.
Features
• Diode Emulation Functionality in deep and deeper sleep
modes for improved light load efficiency
• IMVP-IV™ and IMVP-IV+™ Compliant CORE Regulator
• Single and/or Two-phase Power Conversion
• “Loss-less” Current sensing for improved efficiency and
reduced board area
- Optional Discrete Precision Current Sense Resistor
• Internal Gate-Drive and Boot-Strap Diodes
• Precision CORE Voltage Regulation
- 0.8% system accuracy over temperature
• 6-Bit Microprocessor Voltage Identification Input
• Programmable “Droop” and CORE Voltage Slew Rate to
comply with IMVP-IV™ and IMVP-IV+™ specification
• Direct Interface with System Logic (STP_CPU# and
DPRSLPVR) for Deep and Deeper Sleep modes of
operation
• Easily Programmable voltage setpoints for Initial “Boot”,
Deep Sleep and Deeper Sleep Modes
• Excellent Dynamic Response
- Combined Voltage Feed-Forward and Average Current
Mode Control
• Overvoltage, Undervoltage and Overcurrent Protection
• Power-Good Output with internal blanking during VID and
mode changes
• User programmable Switching Frequency of 250kHz -
1MHz per phase
• Pb-Free Plus Anneal Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6217A
Functional Pin Description
VDD - This pin is used to connect +5V to the IC to supply all
power necessary to operate the chip. The IC starts to
operate when the voltage on this pin exceeds the rising POR
threshold and shuts down when the voltage on this pin drops
below the falling POR threshold.
DACOUT - This pin provides access to the output of the
Digital-to-Analog Converter.
DSV - The voltage on this pin provides the set point for
output voltage during Deep Sleep Mode of operation.
FSET - A resistor from this pin to ground programs the
switching frequency.
PWRCH - This pin selects the number of power channels. A
HIGH logic level on this pin enables 2 channel operation,
and a LOW logic signal enables single channel operation.
EN - This pin is connected to the system signal VR_ON and
provides the enable/disable function for the PWM controller.
DRSEN - This pin connects to system logic “DPRSLPVR”
and enables Deeper Sleep mode of operation when a logic
HIGH is detected on this pin.
DSEN# - This pin connects to system logic “STP_CPU#” and
enables Deep Sleep mode of operation. Deep Sleep is
enabled when a logic LOW signal is detected on this pin.
VID0, VID1, VID2, VID3, VID4, VID5 - These pins are used
as inputs to the 6-bit Digital-to-Analog converter (DAC). VID0
is the least significant bit and VID5 is the most significant bit.
PGOOD - This pin is used as an input and an output and is
tied to the Vccp and Vcc_mch PGOOD signals. During start-
up, this pin is recognized as an input and prevents further
slewing of the output voltage from the “Boot” level until
PGOOD from Vccp and Vcc_mch is enabled High. After
Start-up, this pin has an open drain output used to indicate
the status of the CORE output voltage. This pin is pulled low
when the system output is outside of the regulation limits.
PGOOD includes a timer for power-on delay.
EA+ - This pin is connected to the non-inverting input of the
error amplifier and is used for setting the “Droop” voltage.
COMP - This pin provides connection to the error amplifier
output.
FB - This pin is connected to the inverting input of the error
amplifier.
SOFT - This pin programs the slew rate of VID changes,
Deep Sleep and Deeper Sleep transitions and Soft-Start
after initializing. This pin is connected to ground via a
capacitor, and to EA+ through an external “Droop” resistor.
VBAT - Voltage on this pin provides feed-forward battery
information which adjusts the oscillator ramp amplitude.
ISEN1, ISEN2 - These pins are used as current sense inputs
from the individual converter channel phase nodes.
PHASE1, PHASE2 - These pins are connected to the phase
nodes of channels 1 and 2, respectively.
UG1, UG2 - These pins are the gate-drive outputs to the
high side MOSFETs for channels 1 and 2, respectively.
BOOT1, BOOT2 - These pins are connected to the
bootstrap capacitors, for upper gate-drive, for channels 1
and 2, respectively.
VSSP1, VSSP2 - These pins are connected to the power
ground of channels 1 and 2, respectively.
LG1, LG2 - These pins are the gate-drive outputs to the low
side MOSFETs for channels 1 and 2, respectively.
VDDP - This pin provides a low-esr bypass connection to the
internal gate drivers for the +5V source.
VSEN - This pin is used for remote sensing of the
microprocessor CORE voltage.
DRSV - The voltage on this pin provides the set point for
output voltage during Deeper Sleep Mode of operation.
OCSET - A resistor from this pin to ground sets the
overcurrent protection threshold. The current from this pin
should be between 10µA and 25µA (70kΩ - 175kΩ
equivalent) pull-down resistance.
STV - The voltage on this pin sets the initial Start-Up or
“Boot” voltage.
VSS - This pin provides connection for signal ground.
5 FN9107.3
June 30, 2005
5 Page 
ISL6217A
Active, Deep Sleep and Deeper Sleep Modes
The ISL6217A Multi-Phase Controller is designed to control
the CORE output voltage as per the IMVP-IV™ and
IMVP-IV+™ specifications for Active, Deep Sleep, and
Deeper Sleep Modes of Operation.
After initial Start-up, a logic high signal on DSEN# and a
logic low signal on DRSEN signals the ISL6217A to operate
in Active mode. Refer to Table 2. This mode will recognize
VID code changes and regulate the output voltage to these
command voltages.
TABLE 2. OUTPUT VOLTAGE AS A FUNCTION OF DSEN#
AND DRSEN LOGIC STATES
DSEN# -
STP_CPU#
DRSEN -
DPRSLPVR
MODE OF OUTPUT
OPERATION VOLTAGE
1
0
Active
VID
0
0
Deep Sleep
DSV
0 1 Deeper Sleep DRSV
1 1 Deeper Sleep DRSV
VID[0..5]
VCC_CORE
Current VID Code
<600ns
Current Voltage Level
New VID Code
New Voltage Level
PGOOD HIGH
FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
VID[0..5]
STP_CPU#
(DSEN#)
VCC_CORE
VID Code remains the same
VID Command Voltage
VDeep Sleep
<30us
FIGURE 6. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
VID[0..5]
STP_CPU#
(DSEN#)
DPRSLPVR
(DRSEN)
VCC_CORE
VDeep Sleep
VDeeper Sleep
VID Code remains the same
Deeper Sleep Mode
Short DPRSLP causes
VCC-CORE to ramp up
FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
11 FN9107.3
June 30, 2005
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL6217A.PDF ] | |
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