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PDF CY7C1071DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1071DV33 | |
| Descripción | 32-Mbit (2M x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1071DV33
32-Mbit (2 M × 16) Static RAM
32-Mbit (2 M × 16) Static RAM
Features
■ High speed
❐ tAA = 12 ns
■ Low active power
❐ ICC = 250 mA at 83.3 MHz
■ Low Complementary Metal Oxide Semiconductor (CMOS)
standby power
❐ ISB2 = 50 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Available in Pb-free 48-ball FBGA package
Logic Block Diagram
Functional Description
The CY7C1071DV33 is a high performance CMOS Static RAM
organized as 2,097,152 words by 16 bits. The input and output
pins (I/O0 through I/O15) are placed in a high impedance state
when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH)
■ The write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A20). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A20).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
For a complete list of related documentation, click here.
DATA IN DRIVERS
A(10:0)
2M × 16
RAM ARRAY
IO0–IO7
IO8–IO15
COLUMN DECODER
A(20:11)
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12063 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 18, 2014
1 page  
CY7C1071DV33
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
OUTPUT
Z0 = 50
50
30 pF*
VTH = 1.5 V
(a)
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0 V
90%
GND
10%
RISE TIME:
> 1 V/ns
ALL INPUT PULSES
(c)
HIGH-Z
CHARACTERISTICS:
3.3 V
R1
317
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE (b)
R2
351
90%
10%
FALL TIME:
> 1 V/ns
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
ICCDR
tCDR[5]
VCC for Data Retention
Data Retention Current
VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Chip Deselect to Data Retention
Time
tR[6] Operation Recovery Time
Min Typ Max Unit
2 – –V
– – 50 mA
0–
tRC –
– ns
– ns
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
VDR > 2 V
3.0 V
tCDR tR
CE
Notes
4.
Valid SRAM operation does not
normal SRAM operation begins
occur until the power supplies reach the minimum operating
to include reduction in VDD to the data retention (VCCDR, 2.0
VVD) Dvo(3lt.a0gVe.).
100
s
(tpower)
after
reaching
the
minimum
operating
VDD,
5. Tested initially and after any design or process changes that may affect these parameters.
6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 001-12063 Rev. *J
Page 5 of 14
5 Page 
CY7C1071DV33
Package Diagram
Figure 9. 48-ball FBGA (8 × 9.5 × 1.2 mm) BA48J Package Outline, 51-85191
Document Number: 001-12063 Rev. *J
51-85191 *C
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C1071DV33.PDF ] | |
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