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PDF CY7C1062DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1062DV33 | |
| Descripción | 16 Mbit (512K x 32) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1062DV33
16 Mbit (512 K × 32) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 175 mA at 10 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE1, CE2, and CE3 features
■ Available in Pb-free 119-ball plastic ball grid array (PBGA)
package
Logic Block Diagram
INPUT BUFFERS
A(9:0)
512K x 32
ARRAY
Functional Description
The CY7C1062DV33 is a high performance CMOS Static RAM
organized as 524,288 words by 32 bits.
To write to the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Write Enable (WE) input LOW. If Byte Enable A (BA)
is LOW, then data from IO pins (IO0 through IO7) is written into
the location specified on the address pins (A0 through A18). If
Byte Enable B (BB) is LOW, then data from IO pins (IO8 through
IO15) is written into the location specified on the address pins (A0
through A18). Likewise, BC and BD correspond with the IO pins
IO16 to IO23 and IO24 to IO31, respectively.
To read from the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If the first BA is LOW, then data from the
memory location specified by the address pins appear on IO0 to
IO7. If BB is LOW, then data from memory appears on IO8 to IO15.
Likewise, Bc and BD correspond to the third and fourth bytes.
See Truth Table on page 10 for a complete description of read
and write modes.
The input and output pins (IO0 through IO31) are placed in a high
impedance state when the device is deselected (CE1, CE2, or
CE3 HIGH), the outputs are disabled (OE HIGH), the byte selects
are disabled (BA-D HIGH), or during a write operation (CE1, CE2
and CE3 LOW and WE LOW).
WE
CE1
CE2
CE3
OE
BA
BB
BC
BD
I/O0 – I/O31
COLUMN
DECODER
A(18:10)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05477 Rev.*G
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 13, 2011
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CY7C1062DV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
COUT
Input capacitance
IO capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
JA Thermal resistance
(Junction to ambient)
JC Thermal resistance
(Junction to case)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows. [3]
Max Unit
8 pF
10 pF
119-Ball
PBGA
20.31
8.35
Unit
C/W
C/W
OUTPUT
Z0= 50
50
30 pF*
VTH = 1.5V
(a)
*Capacitive Load consists of all
components of the test environment
3.0V
GND
Rise Time > 1V/ns
All input pulses
90%
10%
(c)
3.3V
R1 317
OUTPUT
5 pF*
*Including jig
and scope
(b)
R2
351
90%
10%
Fall Time:> 1V/ns
Note
3.
Valid
VDD,
SRAM
normal
operation does not occur until the
SRAM operation begins including
power supplies have reached the minimum operating
reduction in VDD to the data retention (VCCDR, 2.0V)
vVoDltDag(3e..0V).
100s
(tpower)
after
reaching
the
minimum
operating
Document Number: 38-05477 Rev.*G
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CY7C1062DV33
Ordering Information
Speed
(ns)
Ordering Code
10 CY7C1062DV33-10BGI
CY7C1062DV33-10BGXI
Package
Diagram
Package Type
51-85115 119-ball Plastic Ball Grid Array (14 × 22 × 2.4 mm)
119-ball Plastic Ball Grid Array (14 × 22 × 2.4 mm) (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 7 C 1 06 2 D V33 - 10 XXX I
Temperature Range:
I = Industrial
Package Type: XXX = BG or BGX
BG = 119-ball PBGA
BGX = 119-ball PBGA (Pb-free)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
2 = Data width × 32-bits
06 = 16-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document Number: 38-05477 Rev.*G
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