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PDF CY7C1069DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1069DV33 | |
| Descripción | 16-Mbit (2M x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1069DV33
16-Mbit (2 M × 8) Static RAM
16-Mbit (2 M × 8) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 175 mA at 100 MHz
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 54-pin thin small outline package (TSOP)
Type II and 48-ball very fine-pitch ball grid array (VFBGA)
packages.
Functional Description
The CY7C1069DV33 is a high performance CMOS Static RAM
organized as 2,097,152 words by 8 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A20).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the
I/O pins. See Truth Table on page 10 for a complete description
of Read and Write modes.
The input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C1069DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball very fine-pitch ball grid array (VFBGA) package.
For a complete list of related documentation, click here.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
AA34
A5
2Mx8
ARRAY
A6
AAA789
COLUMN
DECODER
I/O0 – I/O7
WE
CE2
OE
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05478 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014
1 page  
CY7C1069DV33
Capacitance
Parameter [3]
Description
CIN
COUT
Input capacitance
IO capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
TSOP II
6
8
VFBGA
8
10
Unit
pF
pF
Thermal Resistance
Parameter [3]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
TSOP II
24.18
5.40
VFBGA
28.37
5.79
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [4]
OUTPUT
Z0 = 50
(a)
* Capacitive load consists
of all components of the
test environment
50
30 pF*
VTH = 1.5 V
3.0 V
GND
Rise Time > 1 V/ns
ALL INPUT PULSES
90%
10%
(c)
High Z characteristics
3.3 V
R1 317
OUTPUT
5 pF*
90%
10%
INCLUDING
JIG AND
SCOPE (b)
Fall Time:
> 1 V/ns
R2
351
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4.
Valid
VDD,
SRAM
normal
operation does not occur
SRAM operation begins
iunnctluildthinegproewduecr tsiounppinlieVsDhDatvoetrheeadchaetadrtehteenmtiionnim(VumCCoDpRe,r2a.t0inVg)VvDoDlta(3g.e0.
V).
100
s
(tpower)
after
reaching
the
minimum
operating
Document Number: 38-05478 Rev. *H
Page 5 of 15
5 Page 
CY7C1069DV33
Package Diagrams
Figure 9. 54-pin TSOP Type II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 38-05478 Rev. *H
Page 11 of 15
11 Page | ||
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