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PDF CY7C1051DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1051DV33 | |
| Descripción | 8-Mbit (512K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1051DV33
8-Mbit (512 K × 16) Static RAM
8-Mbit (512K x 16) Static RAM
Features
■ Temperature ranges
❐ –40 °C to 85 °C
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 110 mA at f = 100 MHz
■ Low CMOS standby power
❐ ISB2 = 20 mA
■ 2.0-V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL)-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 48-ball fine ball grid array (FBGA) and
44-pin thin small outline package (TSOP) II packages
Functional Description
The CY7C1051DV33 is a high performance CMOS Static RAM
organized as 512 K words by 16-bits.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data
from I/O pins (I/O0–I/O7), is written into the location specified on
the address pins (A0–A18). If Byte HIGH Enable (BHE) is LOW,
then data from I/O pins (I/O8–I/O15) is written into the location
specified on the address pins (A0–A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte LOW Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0–I/O7. If
Byte HIGH Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
The input/output pins (I/O0–I/O15) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or a write operation (CE LOW, and
WE LOW) is in progress.
The CY7C1051DV33 is available in a 44-pin TSOP II package
with center power and ground (revolutionary) pinout and a
48-ball FBGA package.
Logic Block Diagram
A0
A1
A2
AA34
AA56
AA78
INPUT BUFFER
512 K × 16
ARRAY
COLUMN
DECODER
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00063 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 10, 2014
1 page  
CY7C1051DV33
AC Test Loads and Waveforms
AC characteristics (except High-Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for
all speeds using the test load shown in Figure 3 (c).
Figure 3. AC Test Loads and Waveforms
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50
1.5 V
High-Z Characteristics
3.3 V
R 317
(a)
30 pF*
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
OUTPUT
5 pF
R2
351
(c)
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
ICCDR
tCDR[4]
tR[4]
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Conditions[3]
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Min Max Unit
2.0 –
V
– 20 mA
0 – ns
tRC –
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
VDR > 2 V
3.0 V
tCDR
tR
CE
Notes
3. No inputs may exceed VCC + 0.3 V
4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 001-00063 Rev. *I
Page 5 of 15
5 Page 
CY7C1051DV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and
refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains
a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit
us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
10
12
Ordering Code
CY7C1051DV33-10BAXI
CY7C1051DV33-10ZSXI
CY7C1051DV33-12BAXI
CY7C1051DV33-12ZSXI
Package
Diagram
51-85193
51-85087
51-85193
51-85087
Package Type
48-ball FBGA (Pb-free)
44-pin TSOP II (Pb-free)
48-ball FBGA (Pb-free)
44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7 C 1 05 1 D V33 - XX XXX X
Temperature Range: x = I or E
I = Industrial
Package Type: XXX = BAX or ZSX
BAX = 48-ball FBGA (Pb-free)
ZSX = 44-pin TSOP II(Pb-free)
Speed: XX = 10 ns or 12 ns or 15 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
1 = Data width × 16-bits
05 = 8-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document Number: 001-00063 Rev. *I
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY7C1051DV33.PDF ] | |
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