|
|
PDF CY7C1034DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1034DV33 | |
| Descripción | 6-Mbit (256K x 24) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1034DV33 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
CY7C1034DV33
6-Mbit (256K X 24) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 175 mA at f = 100 MHz
■ Low CMOS standby power
❐ ISB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE1, CE2, and CE3 features
■ Available in Pb-free standard 119-Ball PBGA
Functional Description
The CY7C1034DV33 is a high performance CMOS static RAM
organized as 256K words by 24 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE1 LOW, CE2 HIGH,
and CE3 LOW) while forcing the Write Enable (WE) input LOW.
To read from the device, enable the chip by taking CE1 LOW, CE2
HIGH, and CE3 LOW, while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 IO pins (IO0 to IO23) are placed in a high impedance state
when the device is deselected (CE1 HIGH, CE2 LOW, or CE3
HIGH) or when the output enable (OE) is HIGH during a write
operation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW).
Logic Block Diagram
INPUT BUFFER
A(9:0)
256K x 24
ARRAY
IO0 – IO23
COLUMN
DECODER
A(17:10)
CONTROL LOGIC
CE1, CE2, CE3
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-08351 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 29, 2011
1 page  
CY7C1034DV33
AC Switching Characteristics (continued)
Over the operating range [5]
Parameter
Write Cycle [9, 10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Description
Write cycle time
CE active LOW to write end [3]
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low Z [7]
WE LOW to high Z [7]
–10
Min Max
10 –
7–
7–
0–
0–
7–
5.5 –
0–
3–
–5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Characteristics
Over the operating range
Parameter
Description
Conditions [3]
Min Typ Max Unit
VDR
ICCDR
tCDR [11]
tR [12]
VCC for data retention
Data retention current[9]
Chip deselect to data retention time
Operation recovery time
VCC = 2 V, CE1, CE3 > VCC – 0.2 V,
CE2 < 0.2 V,VIN > VCC – 0.2 V or VIN < 0.2 V
2
–
0
tRC
–
–
–
–
–V
25 mA
– ns
– ns
Figure 2. Data Retention Waveform
VCC
CE
3.0V
tCDR
DATA RETENTION MODE
VDR > 2V
3.0V
tR
Notes
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW. Chip enables must be active and WE must be LOW
to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal
that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 001-08351 Rev. *E
Page 5 of 12
5 Page 
CY7C1034DV33
Document History Page
Document Title: CY7C1034DV33 6-Mbit (256K X 24) Static RAM
Document Number: 001-08351
REV. ECN NO.
Orig. of
Change
Submission
Date
Description of Change
** 469517
NXR
See ECN New data sheet
*A 499604
NXR
See ECN
Added note 1 for NC pins
Changed ICC specification from 150 mA to 185 mA
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics
Table on page 4
*B 1462586 VKN/SFV See ECN Converted from preliminary to final
Updated block diagram
Changed ICC specification from 185 mA to 225 mA
Updated thermal specs
*C 2644842 VKN/PYRS 01/23/09 Replaced Commercial range with the Industrial
Replaced 8 ns speed with 10 ns
*D 3109199 PRAS
12/13/2010 Added Ordering Code Definitions.
Updated Package Diagram.
*E 3388455 TAVA
09/29/2011 Minor text edits. Added Acronyms and Document Conventions.
Updated template.
Document Number: 001-08351 Rev. *E
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY7C1034DV33.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1034DV33 | 6-Mbit (256K x 24) Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |