|
|
PDF CY7C1041D Data sheet ( Hoja de datos )
| Número de pieza | CY7C1041D | |
| Descripción | 4-Mbit (256K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1041D (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
CY7C1041D
4-Mbit (256 K × 16) Static RAM
Features
■ Pin-and function-compatible with CY7C1041B
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 90 mA at 10 ns (Industrial)
■ Low CMOS standby power
❐ ISB2 = 10 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 44-Pin (400-Mil) Molded SOJ and 44-Pin
TSOP II packages
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
INPUT BUFFER
256K x 16
Functional Description[1]
The CY7C1041D is a high-performance CMOS static RAM
organized as 256K words by 16 bits. Writing to the device is
accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O8 to I/O15. See the truth table
at the back of this data sheet for a complete description of read
and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW,
and WE LOW).
The CY7C1041D is available in a standard 44-pin 400-mil-wide
body width SOJ and 44-pin TSOP II package with center power
and ground (revolutionary) pinout.
I/O0–I/O7
I/O8–I/O15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
–10 (Industrial)
10
90
10
–12 (Automotive)[2]
12
95
15
Unit
ns
mA
mA
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05472 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 21, 2011
[+] Feedback
1 page  
CY7C1041D
AC Test Loads and Waveforms[5]
10 ns device
OUTPUT
Z = 50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50 Ω
1.5 V
(a)
High-Z Characteristics:
30 pF*
R1 481Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(c)
R2
255Ω
3.0 V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
(b)
90%
10%
≤ 3 ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73 V
Switching Characteristics[6] Over the Operating Range
Parameter
Read Cycle
tpower
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Description
VCC(typical) to the First Access[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[8, 9]
CE LOW to Low Z[9]
CE HIGH to High Z[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
–10 (Industrial)
Min Max
100
10
10
3
10
5
0
5
3
5
0
10
5
0
5
–12 (Automotive)
Min Max
100
12
12
3
12
6
0
6
3
6
0
12
6
0
6
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c)
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device.
Document #: 38-05472 Rev. *F
Page 5 of 14
[+] Feedback
5 Page 
Package Diagrams
Figure 8. 44-Pin (400-Mil) Molded SOJ (51-85082)
CY7C1041D
Figure 9. 44-pin TSOP II (51-85087)
51-85082 *C
Document #: 38-05472 Rev. *F
51-85087 *B
51-85087 *C
Page 11 of 14
[+] Feedback
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C1041D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1041 | 256K x 16 Static RAM | Cypress Semiconductor |
| CY7C1041B | 256K x 16 Static RAM | Cypress Semiconductor |
| CY7C1041BV33 | 256K x 16 Static RAM | Cypress Semiconductor |
| CY7C1041CV33 | 256K x 16 Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |