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PDF CY7C1041 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1041 | |
| Descripción | 256K x 16 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1041
256K x 16 Static RAM
Features
• High speed
— tAA = 15 ns
• Low active power
— 1430 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description
The CY7C1041 is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
Logic Block Diagram
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041 is available in a standard 44-pin 400-mil-wide
body width SOJ and 44-pin TSOP II package with center pow-
er and ground (revolutionary) pinout.
Pin Configuration
INPUT BUFFER
A0
A1
A2
A3 256K x 16
A4 ARRAY
A5 1024 x 4096
A6
A7
A8
COLUMN
DECODER
I/O0 – I/O7
I/O8 – I/O15
BHE
WE
CE
OE
BLE
1041–1
Selection Guide
7C1041-12
Maximum Access Time (ns)
12
Maximum Operating Current (mA)
280
Maximum CMOS Standby Current Com’l
(mA)
Com’l L
3
0.5
Ind’l 6
Shaded areas contain preliminary information.
7C1041-15
15
260
3
0.5
6
SOJ
TSOP II
Top View
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
1041–2
7C1041-17
17
250
3
0.5
6
7C1041-20
20
230
3
0.5
6
7C1041-25
25
220
3
0.5
6
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999
1 page  
CY7C1041
Switching Characteristics[4] Over the Operating Range (continued)
Parameter
Description
READ CYCLE
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
tPU CE LOW to Power-Up
tPD CE HIGH to Power-Down
tDBE Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
WRITE CYCLE[7, 8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[5, 6]
Byte Enable to End of Write
7C1041-20
Min.
Max.
20
20
3
20
8
0
8
3
8
0
20
8
0
8
20
13
13
0
0
13
9
0
3
8
13
7C1041-25
Min.
Max.
25
25
5
25
10
0
10
5
10
0
25
10
0
10
25
15
15
0
0
15
10
0
5
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions[10]
VDR
ICCDR
VCC for Data Retention
Data Retention Current
Com’l L
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
tCDR[3]
tR[9]
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes:
9. tr < 100 µs for all speeds.
10. No input may exceed VCC + 0.5V.
Min.
2.0
0
Max.
200
See Note 9
Unit
V
µA
µA
µA
ns
5
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