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PDF CY7C1024DV33 Data sheet ( Hoja de datos )

Número de pieza CY7C1024DV33
Descripción 3-Mbit (128K x 24) Static RAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CY7C1024DV33 Hoja de datos, Descripción, Manual

CY7C1024DV33
3-Mbit (128 K × 24) Static RAM
Features
I Highspeed
Ë tAA = 10 ns
I Low activepower
Ë ICC = 175 mA at f= 100 MHz
I Low CMOS standbypower
Ë ISB2 = 25 mA
I Operatingvoltages of3.3 ±0.3 V
I 2.0 V data retention
I Automatic power-downwhendeselected
I Transistor-transistorlogic (TTL) compatibleinputs andoutputs
I EasymemoryexpansionwithCE1, CE2, andCE3 features
I AvailableinPb-freestandard119-ballPBGA
FunctionalDescription
TheCY7C1024DV33 is a highperformanceCMOS static RAM
organizedas 128 K words by24 bits. This devicehas an
automatic power-downfeaturethat significantlyreduces power
consum ption when deselected.
Towritetothedevice, enablethechip(CE1 LOW, CE2 HIGH,
andCE3 LOW), whileforcingtheWriteEnable(WE) input LOW.
Toreadfrom thedevice, enablethechipbytakingCE1 LOW, CE2
HIGH, andCE3 LOW whileforcingtheOutput Enable(OE) LOW
andtheWriteEnable(WE) HIGH. SeetheTruthTableonpage
7 fora completedescriptionofReadandWritemodes.
The24 I/O pins (I/O0 toI/O23) areplacedina highimpedance
statewhenthedeviceis deselected(CE1 HIGH, CE2 LOW, or
CE3 HIGH) orwhentheoutput enable(OE) is HIGH duringa
writeoperation. (CE1 LOW, CE2 HIGH, CE3 LOW, andWE
LOW).
Logic Block Diagram
INPUT BUFFER
A(9:0)
128K x24
ARRAY
I/O0 –I/O23
COLUMN
DECODER
A(16:10)
CONTROL LOGIC
CE1, CE2, CE3
WE
OE
CypressSem iconductorCorporation • 198 ChampionCourt
Document Number:001-08353 Rev. *E
• SanJose, CA 95134-1709 • 408-943-2600
RevisedSeptember29, 2011

1 page




CY7C1024DV33 pdf
CY7C1024DV33
AC Switching Characteristics (continued)
Overthe Operating Range [5]
Param eter
Description
W riteCycle[9, 10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write cycle tim e
CE activeLOW towriteend[3]
Address setuptowriteend
Address holdfrom writeend
Address setuptowritestart
WE pulsewidth
Data setuptowriteend
Data holdfrom writeend
WE HIGH tolow Z [7]
WE LOW tohighZ [7]
DataRetention Characteristics
Overthe Operating Range
Param eter
Description
VDR
ICCDR
VCC fordata retention
Data retentioncurrent
tCDR [11]
tR [12]
Chipdeselect todata retentiontime
Operation recoverytim e
Conditions [3]
VCC =2 V, CE > VCC –0.2 V,
VIN > VCC –0.2 V orVIN < 0.2 V
DataRetention W aveform
VCC
CE
3.0 V
tCDR
DATA RETENTION MODE
VDR > 2 V
–10
Min Max
10 –
7–
7–
0–
0–
7–
5.5 –
0–
3–
–5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min Typ Max Unit
2 ––V
– – 25 mA
0–
tRC
– ns
– ns
3.0 V
tR
Notes
9. Theinternalwritetimeofthememoryis definedbytheoverlapofCE1 andCE2 andCE3 LOW andWE LOW. Chipenables must beactiveandWE must beLOW to
initiatea write. Thetransitionofanyofthesesignals terminatethewrite. Theinput data setupandholdtimingis referencedtotheleadingedgeofthesignalthat
terminates thewrite.
10. Theminimum writecycletimeforWriteCycleNo. 3 (WE controlled, OE LOW) is thesum oftHZWE andtSD.
11. Testedinitiallyandafteranydesignorprocess changes that mayaffect theseparameters.
12. Fulldeviceoperationrequires linearVCC rampfrom VDR toVCC(min) > 50 Ps orstableat VCC(min) > 50 Ps.
Document Number:001-08353 Rev. *E
Page5 of12

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CY7C1024DV33 arduino
CY7C1024DV33
Docum entHistoryPage
Docum entTitle:CY7C1024DV33,3-Mbit(128K × 24)StaticRAM
Docum entNum ber:001-08353
Rev. ECN No.
Orig.of
Change
Subm ission
Date
Description ofChange
** 469517
NXR
SeeECN New data sheet
*A 499604
NXR
See ECN
Addednote1 forNC pins
ChangedICC specificationfrom 150 mA to185 mA
UpdatedTest ConditionforICC inDC ElectricalCharacteristics table
AddednotefortACE, tLZCE, tHZCE, tPU, tPD, tSCE inAC SwitchingCharacteristics Table
on page 4
*B 1462586 VKN/SFV
See ECN
Convertedfrom preliminarytofinal
Updated blockdiagram
ChangedICC specificationfrom 185 mA to225 mA
Updated therm alspecs
*C 2604677 VKN/PYRS 11/12/08 RemovedCommercialoperatingrange, AddedIndustrialoperatingrange
Removed8 ns speedbin, Added10 ns speedbin
*D 3109199
PRAS
12/13/2010 AddedOrderingCodeDefinitions.
Updated Package Diagram .
*E 3388080
TAVA
09/29/2011 Minortechnicaledits. AddedAcronyms andDocument Conventions.
Updated tem plate.
Document Number:001-08353 Rev. *E
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