PDF PMS307416A Data sheet ( Hoja de datos )

Número de pieza	PMS307416A
Descripción	2048K Words x 16 Bits x 4 Banks (128-MBIT) Synchronous Dynamic RAM
Fabricantes	PM Tech
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No Preview Available ! πPM Tech PMS307416A 2048K Words x 16 Bits x 4 Banks (128-MBIT) Synchronous Dynamic RAM Features z Clock frequency: 166, 133 MHz z Fully synchronous; all signals referenced to a positive clock edge z Four banks operation z Single 3.3V power supply z LVTTL interface z Programmable burst length -- (1, 2, 4, 8, full page) z Programmable burst sequence: Sequential/Interleave z 4096 refresh cycles every 64 ms z Random column address every clock cycle z Programmable /CAS latency (2, 3 clocks) z Burst read/write and burst read/single write operations capability z Burst termination by burst stop and precharge command z Byte controlled by LDQM and UDQM z Packages 400-mil 54-pin TSOP-II z Lead-free package Overview The PMS307416 is a high-speed CMOS synchronous DRAM containing 134,217,728 bits. It is organized as 4 Banks of 2048K Words x 16 Bits DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Commercial Range: 0°C to 70°C Frequency Speed Part No. 166MHz 6ns PMS307416ATR-6CN 133MHz 7.5ns PMS307416ATR-75CN Package 400-Mil TSOP II Lead-free Pin Assignment VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 VSS 53 DQ15 52 VSSQ 51 DQ14 50 DQ13 49 VDDQ 48 DQ12 47 DQ11 46 VSSQ 45 DQ10 44 DQ9 43 VDDQ 42 DQ8 41 VSS 40 NC 39 UDQM 38 CLK 37 CKE 36 NC 35 34 33 32 31 30 29 28 A11 A9 A8 A7 A6 A5 A4 VSS Pin Descriptions A0-A11 A0-A11 BA0, BA1 A0-A8 DQ0-DQ15 CLK CKE /CS /RAS Address Input Row Address Input Bank Select Address Column Address Input Data DQ System Clock Input Clock Enable Chip Select Row Address Strobe Command /CAS /WE LDQM UDQM VDD VSS VDDQ VSSQ NC Column Address Strobe Command Write Enable Lower Byte, Input/Output Mask Lower Byte, Input/Output Mask Power Ground Power Supply for DQ Pin Ground for DQ Pin No Connection This document is a general product description and subject to change without notice. 1 page πPM Tech PieceMakers Confidential and Proprietary PMS307416ATR DC Characteristics (VDD = 3.3V ± 0.3V, TA = 0~70°C) Parameter/Test condition Operating Current tRC ≥ tRC(min), Outputs Open One bank active Precharge Standby Current in power down mode tCK = tck(min), CKE ≤ VIL(max) Precharge Standby Current in power down mode tCK = ∞, CKE ≤ VIL(max) Precharge Standby Current in non-power down mode tCK = tck(min), /CS ≥ VIH(min), CKE ≥ VIH Input signals are changed very 2CLKs Precharge Standby Current in non-power down mode tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH Active Standby Current in power down mode tCK = tck(min), CKE ≤ VIL(max) Active Standby Current in power down mode tCK = ∞, CKE ≤ VIL(max) Active Standby Current in non-power down mode tCK = tck(min), CKE ≥ VIH(min), /CS ≥ VIH(min) Input signals are changed very 2clks Active Standby Current in non-power down mode CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ Operating Current (Burst mode) tCK =tCK(min), Outputs Open, All banks active Refresh Current tRC ≥ tRC(min) Self Refresh Current CKE ≤ 0.2V Symbol IDD1 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4 IDD5 IDD6 Max. -6 -75 120 100 5 2 35 20 35 20 60 30 140 125 150 135 5 Unit mA Note: 1. IDD1, IDD2N, IDD2P, IDD3N, IDD4, and IDD5 depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 2. IDD1 and IDD4 depend on the output loading. Specified values are obtained with the output open. Rev 0.1 5 February 2010 5 Page πPM Tech PieceMakers Confidential and Proprietary PMS307416ATR Command Truth Table(1,2) Command Symbol CKEn-1 CKEn /CS /RAS /CAS /WE DQM BA0–BA1 A10 A0-A11 DQ Mode Register Set(3,4) MRS H X LL L LX OP CODE X Auto Refresh(5) REF H H LL LHX X X X High-Z Self Refresh(5,6) SREF H L L L L H X X X X High-Z Precharge Selected Bank PRE H X LL HLX V LX X Precharge All Banks PALL H X LL HLX X HX X Bank Activate(7) ACT H X LL HHX V Row address X Write Write and Auto Precharge(8) Read(8) WRIT WRITA READ Read and Auto precharge(8) READA H H H H X LH L L X X LH L L X X LH L HX X LH L HX VL X Column V H address(18) X V L Column X V H address(18) X Burst Stop(9) BST H X LH H L X X XX X No Operation NOP H X L H H H X X X X X Device Deselect DESL H X H X X X X X XX X Clock Suspend Mode SBY L X XX X X X X XX X Data Write/Output Enable ENB H X XX X X L X X X Active Data Mask/Output Disable MASK H X XX X X H X X X High-Z DQM Truth Table(1,2) Command Data Write/Output Enable Data Mask/Output Disable Upper Byte Data Write/Output Enable Lower Byte Data Write/Output Enable Upper Byte Data Mask/Output Disable Lower Byte Data Mask/Output Disable Symbol ENB MASK ENBU ENBL MASKU MASKL CKEn-1 H H H H H H CKEn X X X X X X UDQM L H L X H X LDQM L H X L X H Rev 0.1 11 February 2010 11 Page

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