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PDF MCIMX27L Data sheet ( Hoja de datos )
| Número de pieza | MCIMX27L | |
| Descripción | Multimedia Applications Processor | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Technical Data
Document Number: MCIMX27EC
Rev. 1.8, 1/2013
i.MX27 and i.MX27L
i.MX27 and i.MX27L
Data Sheet
Multimedia Applications
Processor
Package Information
Plastic Package
Case 1816-01
(MAPBGA–404)
Case 1931-04
(MAPBGA-473)
Ordering Information
See Table 1 on page 4 for ordering information.
1 Introduction
The i.MX27 and i.MX27L (MCIMX27/MX27L)
multimedia applications processors represents the next
step in low-power, high-performance application
processors. Unless otherwise specified, the material in
this data sheet is applicable to both the i.MX27 and
i.MX27L processors and referred to singularly
throughout this document as i.MX27.
The i.MX27L does not include the following features:
ATA-6 HDD Interface, Memory Stick Pro, VPU:
MPEG-4/ H.263/H.264 HW encoder/decoder, and
eMMA (PrP processing, CSC, deblock, dering).
Based on an ARM926EJ-S™ microprocessor core, the
i.MX27/27L processor provides the performance with
low power consumption required by modern digital
devices such as the following:
• Feature-rich cellular phones
• Portable media players and mobile gaming
machines
• Personal digital assistants (PDAs) and wireless
PDAs
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . 4
2. Functional Description and Application Information . . . . 4
2.1. ARM926 Microprocessor Core Platform . . . . . . . . 4
2.2. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3. Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . 9
3. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1. Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . 35
3.2. EMI Pins Multiplexing . . . . . . . . . . . . . . . . . . . . . 35
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 40
4.1. i.MX27/iMX27L Chip-Level Conditions . . . . . . . . 40
4.2. Module-Level Electrical Specifications . . . . . . . . 43
4.3. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 54
5. Package Information and Pinout . . . . . . . . . . . . . . . . 109
5.1. Full Package Outline Drawing (17 mm × 17 mm) 109
5.2. Pin Assignments (17 mm × 17 mm) . . . . . . . . . 110
5.3. Full Package Outline Drawing (19 mm × 19 mm) 129
5.4. Pin Assignments (19 mm × 19 mm) . . . . . . . . . 130
6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . 150
7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
© Freescale Semiconductor, Inc., 2008-2012. All rights reserved.
1 page  
Functional Description and Application Information
The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other
application-specific hardware acceleration to be added. The ARM926EJ-S processor implements ARM
architecture version 5TEJ.
The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports
of the MAX, are designed to support connections to multiple AHB masters external to the platform. An
external arbitration AHB control module is needed if multiple external masters are desired to share an
ARM926 Platform alternate bus master port. However, the alternate bus master ports on the platform
support seamless connection to a single master with no external interface logic required.
A primary AHB MUX (PAHBMUX) module performs address decoding, read data muxing, bus
watchdog, and other miscellaneous functions for the primary AHB within the platform. A clock control
module (CLKCTL) is provided to support a power-conscious design methodology, as well as
implementation of several clock synchronization circuits.
2.1.1 Memory System
The ARM926EJ-S complex includes 16-Kbyte Instruction and 16-Kbyte Data caches. The embedded
45-Kbyte SRAM (VRAM) can be used to avoid external memory accesses or it can be used for
applications. There is also a 24-Kbyte ROM for bootstrap code.
2.2 Module Inventory
Table 2 shows an alphabetical listing of the modules in the i.MX27/MX27L multimedia applications
processors. A cross-reference to each module’s section and page number goes directly to a more detailed
module description for additional information.
Table 2. Digital and Analog Modules
Block Mnemonic Block Name
Functional
Grouping
Brief Description
Section/
Page
1-Wire®
1-Wire Interface
Connectivity
Peripheral
The 1-Wire module provides bi-directional communication
between the ARM926EJ-S and the Add-Only-Memory EPROM
(DS2502). The 1-Kbit EPROM is used to hold information
about battery and communicates with the ARM926 Platform
using the IP interface.
2.3.1/9
AIPI
AHB-Lite IP Bus Control The AIPI acts as an interface between the ARM Advanced
2.3.2/10
Interface
High-performance Bus Lite. (AHB-Lite) and lower bandwidth
Module
peripherals that conforms to the IP Bus specification, Rev 2.0.
AITC
ARM9EJ-S
Interrupt
Controller
Bus Control
AITC is connected to the primary AHB as a slave device. It
generates the normal and fast interrupts to the ARM926EJ-S
processor.
2.3.3/10
ARM926EJS ARM926EJ-S
CPU
The ARM926EJ-S (ARM926) is a member of the ARM9 family 2.3.4/10
of general-purpose microprocessors targeted at multi-tasking
applications.
ATA
Advanced
Connectivity The ATA block is an AT attachment host interface. It interfaces 2.3.5/11
Technology(AT) Peripheral with IDE hard disc drives and ATAPI optical disc drives.
Attachment
Freescale Semiconductor
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
5
5 Page 
Functional Description and Application Information
The ARM926EJ-S processor is a fully synthesizable macrocell, with a configurable memory system. Both
instruction and data caches will be 16 kbytes on the platform. The cache is virtually accessed and virtually
tagged. The data cached has physical tags as well. The MMU provides virtual memory facilities which are
required to support various platform operating systems such as Symbian OS, Windows CE, and Linux. The
MMU contains eight fully associative TLB entries for lockdown and 64 set associative entries. Refer to
the ARM926EJ-S Technical Reference Manual for more information.
2.3.5 Advanced Technology Attachment (ATA)
The Advanced Technology Attachment (ATA) host controller complies with the ATA/ATAPI-6
specification. The primary use of the ATA host controller is to interface with IDE hard disc drives and
Advanced Technology Attachment Packet Interface (ATAPI) optical disc drives. It interfaces with the ATA
device over a number of ATA signals.
This host controller supports interface protocols as specified in ATA/ATAPI-6 standard, as follows:
• PIO mode 0, 1, 2, 3, and 4
• Multiword DMA mode 0, 1, and 2
• Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher
• Ultra DMA mode 5 with bus clock of 80 MHz or higher
Before accessing the ATA bus, the host must program the timing parameters to be used on the ATA bus.
The timing parameters control the timing on the ATA bus. Most timing parameters are programmable as a
number of clock cycles (1 to 255). Some are implied. All of the ATA device-internal registers are visible
to users, and they are defined as mirror registers in ATA host controller. As specified in ATA/ATAPI-6
standard, all the features/functions are implemented by reading/writing to the device’s internal registers.
There are basically two protocols that can be active at the same time on the ATA bus, as follows:
• The first and simplest protocol (PIO mode access) can be started at any time by the ARM926 to
the ATA bus. The PIO mode is a slow protocol, mainly intended to be used to program an ATA disc
drive, but also can be used to transfer data to/from the disc drive.
• The second protocol is the DMA mode access. DMA mode is started by the ATA interface after
receiving a DMA request from the drive, and only if the ATA interface has been programmed to
accept the DMA request. In DMA mode, either multiword-DMA or ultra-DMA protocol is used
on the ATA bus. All transfers between FIFO and the host IP or DMA IP bus are zero wait states
transfer, so a high-speed transfer between FIFO and DMA/host bus is possible.
2.3.6 Digital Audio MUX (AUDMUX)
The Digital Audio MUX (AUDMUX) provides programmable interconnecting for voice, audio, and
synchronous data routing between host serial interfaces—for example, SSI, SAP, and peripheral serial
interfaces—such as, audio and voice codecs. The AUDMUX allows audio system connectivity to be
modified through programming, as opposed to altering the design of the system into which the chip is
designed. The design of the AUDMUX allows multiple simultaneous audio/voice/data flows between the
ports in point-to-point or point-to-multipoint configurations.
Freescale Semiconductor
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
11
11 Page | ||
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