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PDF TLE7209-3R Data sheet ( Hoja de datos )
| Número de pieza | TLE7209-3R | |
| Descripción | 7A H-Bridge | |
| Fabricantes | Infineon | |
| Logotipo |  |
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7 A H-Bridge for DC-Motor Applications
TLE7209-3R
1 Overview
1.1 Features
• Operating supply voltage 5 V to 28 V
• Typical RDSon = 150 mΩ for each output transistor
(at 25 °C)
• Continuous DC load current 5 A (TC < 100 °C)
• Output current limitation at typ. 6.6 A ± 1.1 A
• Short circuit shut-down for output currents over 8 A
• Logic- inputs TTL/CMOS-compatible
• Output switching frequency up to 30 kHz
• Rise and fall times optimized for 0.5-2 kHz
• Over-temperature protection
• Short circuit protection
• Undervoltage disable function
• Diagnostic by SPI or Status-Flag (configurable)
• Enable and Disable inputs
• PG-DSO-20-65 power package
• Green Product (RoHS compliant)
Functional Description
The TLE7209-3R is an intelligent full H-Bridge, designed for the control of DC and
stepper motors in safety critical applications and under extreme environmental
conditions.
The H-Bridge is protected against over-temperature and short circuits and has an under
voltage lockout for all the supply voltages “VS” (main DC power supply). All malfunctions
cause the output stages to go tristate.
The device is configurable by the DMS pin. When grounded, the device gives diagnostic
information via a simple error flag. When supplied with VCC = 5 V, the device works in
SPI mode. In this mode, detailed failure diagnosis is available via the serial interface.
Type
TLE7209-3R
Data Sheet
Package
PG-DSO-20-65
1
Rev. 1.0, 2014-02-03
1 page  
TLE 7209-3R
2 Circuit Description
Circuit Description
2.1 Control Inputs
The bridge is controlled by the Inputs IN1, IN2, DIS and EN as shown in Table 2. The
outputs OUT1 and OUT2 are set to High or Low by the parallel inputs IN1 and IN2,
respectively. In addition, the outputs can be disabled (set to tristate) by the Disable and
Enable inputs DIS and EN.
Inputs IN1, IN2 and DIS have an internal pull-up. Input EN has an internal pull-down.
Table 2
Pos.
Functional Truth Table
DIS EN IN1 IN2 OUT1 OUT2 SF1) SPI2)
DIA_REG
1. Forward
2. Reverse
L HHL H
L HL HL
L H see
H H Chapter 2.4.2
3. Free-wheeling low
L HL L L
LH
4. Free-wheeling high
L HHHH
HH
5. Disable
HXXXZ
ZL
6. Enable
XL XXZ
ZL
7. IN1 disconnected
L HZ XH
XH
8. IN2 disconnected
L HXZ X
HH
9. DIS disconnected
ZXXXZ
ZL
10. EN disconnected
XZXXZ
ZL
11. Current limit. active L H X X Z
ZH
12. Under Voltage
XXXXZ
ZL
13. Over-temperature
XXXXZ
ZL
14. Over-current
XXXXZ
ZL
1) If Mode “Status-Flag” is selected (see Chapter 2.4)
2) If Mode “SPI-Diagnosis” is selected (see Chapter 2.4)
Data Sheet
5 Rev. 1.0, 2014-02-03
5 Page 
TLE 7209-3R
Circuit Description
6. Because only read access is used in the TLE7209-3R, the SDI data-bits (2nd byte)
are not used
7. Invalid instruction/access:
An instruction is invalid if an unused instruction code is detected (see tables with SPI
instructions). In case an unused instruction code occurred, the data byte “ffhex” (no
error) will be transmitted after having sent the verification byte. This transmission
takes place within the same SPI-frame that contained the unused instruction byte. In
addition any transmission is invalid if the number of SPI clock pulses (falling edge)
counted during active CSN differs from exactly 16 clock pulses. If an invalid instruction
is detected, bit TRANS_F in the following verification byte (next SPI transmission) is
set to HIGH. The TRANS_F bit must not be cleared before it has been sent to the
microcontroller.
8. Transfer error bit TRANS_F:
The bit TRANS_F indicates an error during the previous transfer. An error is
considered to have occurred when an invalid command was sent, the number of SPI
clock pulses (falling edge) counted during active CSN was less than or greater than
16 clock pulses, or SPI clock (SCK) was logical high during falling edge of CSN.
Data Sheet
11 Rev. 1.0, 2014-02-03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TLE7209-3R.PDF ] | |
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