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PDF LTC4101 Data sheet ( Hoja de datos )
| Número de pieza | LTC4101 | |
| Descripción | Smart Battery Charger Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Single Chip Smart Battery Charger Controller
■ 100% Compliant (Rev. 1.1) SMBus Support Allows
for Operation with or without Host
■ Up to 4A Charging Current Capability
■ High Efficiency Synchronous Buck Charger
■ VBAT Optimized 3V to 5.5V
■ SMBus Accelerator Improves SMBus Timing
■ Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
■ 0.5V Dropout Voltage; Maximum Duty Cycle > 98%
■ AC Adapter Current Limit Maximizes Charge Rate
■ ±0.8% Voltage Accuracy; ±4% Current Accuracy
■ 10-Bit DAC for Charge Current Programming
■ 11-Bit DAC for Charger Voltage Programming
■ User-Selectable Overvoltage and Overcurrent Limits
■ High Noise Immunity SafetySignal Sensor
■ Available in a 24-UPin SSOP Package
APPLICATIO S
■ Portable Instruments and Computers
■ Data Storage Systems and Battery Backup Servers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners. Protected by U.S. Patents
including 6650174, 5723970.
LTC4101
Smart Battery
Charger Controller
DESCRIPTIO
The LTC®4101 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construc-
tion of an SBS compliant system. The LTC4101 imple-
ments a Level 2 charger function whereby the charger can
be programmed by the battery or by the host. A SafetySignal
on the battery being charged is monitored for tempera-
ture, connectivity and battery type information. The SMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to
it, including SafetySignal status (via the ChargerStatus
command). The charger also provides an interrupt to the
host whenever a status change is detected (e.g., battery
removal, AC adapter connection).
Charging current and voltage are restricted to chemistry-
specific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Addi-
tionally, the maximum average current from the AC adapter
is programmable to avoid overloading the adapter when
simultaneously supplying load current and charging
current. When supplying system load current, charging
current is automatically reduced to prevent adapter
overload.
TYPICAL APPLICATIO
DCIN
9V to 12V, 2A
CHGEN
ACP
3V
TO 5.5V
1.13k
54.9k
6.04k
1.21k
0.1µF
17 LTC4101 5
VDD DCIN
11 4
DCDIV
INFET
6
CHGEN
24
CLP
10
ACP
23
CLN
71
SMBALERT TGATE
9
SCL
3
BGATE
8
SDA
2
PGND
15
THB
21
CSP
16
THA
22
BAT
13
ILIM
14
VLIM
20
10k IDC
18
VSET
19
ITH
12
GND
0.068µF
0.1µF 0.05Ω
VBAT
< 5.5V
> 5.5V
PART
LTC4101
LTC4100
5k
5µF 0.1Ω 1%
SYSTEM LOAD
SMART BATTERY
24µH
5µF
6.04k
0.12µF
0.0015µF
0.03µF 100Ω
0.1µF
SMBALERT#
SMBCLK
SMBDAT
SafetySignal
Figure 1. 1A Smart Battery Charger
SMBCLK
SMBDAT
4101 F01a
4101f
1
1 page  
LTC4101
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Logic Levels
VIL SCL/SDA Input Low Voltage
VDD = 3V and VDD = 5.5V
●
VIH SCL/SDA Input High Voltage
VDD = 3V and VDD = 5.5V
● 2.1
VOL SDA Output Low Voltage
IPULL-UP = 350µA
●
IIL SCL/SDA Input Current
VSDA, VSCL = VIL
–1
IIH SCL/SDA Input Current
VSDA, VSCL = VIH
–1
VOL SMBALERT Output Low Voltage
IPULL-UP = 500µA
●
SMBALERT Output Pull-Up Current
VSMBALERT = VOL
–17.5
ILEAK
SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV
● –2
VOL CHGEN Output Low Voltage
IOL = 100µA
●
CHGEN Output Pull-Up Current
VCHGEN = VOL
–17.5
VIL CHGEN Input Low Voltage
●
VIH CHGEN Input High Voltage
VDD = 3V
VDD = 5.5V
● 2.5
Power-On Reset Duration
VDD Ramp from 0V to >3V in <5µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
–10
–10
3.9
100
0.8
0.4
1
1
0.4
–3.5
2
0.5
–3.5
0.9
V
V
V
µA
µA
V
µA
µA
V
µA
V
V
V
µs
tHIGH
tLOW
tR
tF
tSU:STA
tHD:STA
tHD:DAT
SCL Serial Clock High Period
SCL Serial Clock Low Period
SDA/SCL Rise Time
SDA/SCL Fall Time
Start Condition Setup Time
Start Condition Hold Time
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k,
VDD = 3V and VDD = 5.5V
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k,
VDD = 3V and VDD = 5.5V
CLOAD = 250pF, RPU = 9.31k, VDD = 3V
and VDD = 5.5V
CLOAD = 250pF, RPU = 9.31k, VDD = 3V
and VDD = 5.5V
VDD = 3V and VDD = 5.5V
VDD = 3V and VDD = 5.5V
VDD = 3V and VDD = 5.5V
●
●
●
●
●
●
●
4
4.7
4.7
4
300
15000
1000
300
µs
µs
ns
ns
µs
µs
ns
tTIMEOUT
Time Between Receiving Valid
ChargingCurrent() and
ChargingVoltage() Commands
VDD = 3V and VDD = 5.5V
● 140 175 210
sec
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4101E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Current accuracy dependent upon circuit compensation and sense
resistor.
Note 6: CTH is defined as the sum of capacitance on THA, THB and
SafetySignal.
Note 7: The corresponding overrange bit will be set when a HEX value
greater than or equal to this value is used.
4101f
5
5 Page 
U
OPERATIO
to set the bottom MOSFET on time. The result is quasi-
constant frequency operation: the converter frequency
remains nearly constant over a wide range of output
voltages. This activity is diagrammed in Figure 3.
OFF
TGATE
ON
ON
BGATE
OFF
INDUCTOR
CURRENT
tOFF
TRIP POINT SET
BY ITH VOLTAGE
4101 F01
Figure 3.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by the IDAC at the IDC pin and adjusts
ITH for the desired voltage across RSENSE.
The voltage at BAT is divided down by an internal resistor
divider set by the VDAC and is used by error amp EA to
decrease ITH if the divider voltage is above the 1.19V
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH
voltage to reduce charging current.
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries that “load dump” themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
PWM Watchdog Timer
There is a watchdog timer that observes the activity on the
TGATE pin. If TGATE stops switching for more than 40µs,
the watchdog activates and turns off the top MOSFET for
about 400ns. The watchdog engages to prevent very low
frequency operation in dropout – a potential source of audible
noise when using ceramic input and output capacitors.
LTC4101
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures initial
current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 1ms.
SMBus Interface
All communications over the SMBus are interpreted by the
SMBus interface block. The SMBus interface is a SMBus
slave device. All internal LTC4101 registers may be up-
dated and accessed through the SMBus interface, and
charger controller as required. The SMBus protocol is a
derivative of the I2CTM bus (Reference “I2C-Bus and How
to Use It, V1.0” by Philips, and “System Management Bus
Specification,” Version 1.1, from the SBS Implementers
Forum, for a complete description of the bus protocol
requirements.)
All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
falling edge of SCL. Detection of an SMBus Stop condition,
or power-on reset via the VDD power-fail, will reset the
SMBus interface to an initial state at any time.
The LTC4101 command set is interpreted by the SMBus
interface and passed onto the charger controller block as
control signals or updates to internal registers.
Description of Supported Battery Charger Functions
The functions are described as follows (see Table 1 also):
FunctionName() 'hnn (command code)
Description: A brief description of the function.
Purpose: The purpose of the function, and an example
where appropriate.
• SMBus Protocol: Refer to Section 5 of the Smart
Battery Charger specification for more details.
I2C is a trademark of Philips Electronics N.V.
*http://www. SBS-FORUM.org
4101f
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11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC4101.PDF ] | |
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