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PDF ML610Q102 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q102 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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ML610Q101/ML610Q102
8-bit Microcontroller
FEDL610Q101-01
Issue Date: Jan. 23, 2013
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers, PWM, UART,
voltage level supervisor (VLS) function, and 10-bit successive approximation type A/D converter, are incorporated around 8-bit
CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel
processing.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic
operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
30.5μs (@32.768kHz system clock)
0.122μs (@8.192MHz system clock)
• Internal memory
− ML610Q101 : Internal 4Kbyte Flash ROM (2K×16 bits) (including unusable 32 byte test data area)
− ML610Q102 : Internal 6Kbyte Flash ROM (3K×16 bits) (including unusable 32 byte test data area)
− Internal 256byte data RAM (256×8 bits)
• Interrupt controller
− 1 non-maskable interrupt source (Internal source: 1)
− 21 maskable interrupt sources (Internal sources: 16, External sources: 5)
• Time base counter (TBC)
− Low-speed time base counter ×1 channel
− High-speed time base counter ×1 channel
• Watchdog timer (WDT)
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timer
− 8 bits × 6 channels (16-bit configuration available)
− Support Continuos timer mode/one shot timer mode
− Timer start/stop function by software or external trigger input
1/21
1 page  
ML610Q102 Block Diagram
Figure 2 show the block diagram of the ML610Q102.
"*" indicates secondary function, tertiary function or quaternary function of each port.
FEDL610Q101 -01
ML610Q101/ML610Q102
VDD
VSS
RESET_N
TEST
AIN0*
to
AIN5*
CMP0P*
CMP0M*
CMP0OUT*
CMP0POUT*
CMP0NOUT*
CMP1P*
CMP1OUT*
EPSW1～3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U8/100)
GREG
0～15
ELR1～3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
RESET &
TEST
OSC
Power
10bit-ADC
INT
1
Analog
Comparator
×2
INT
2
RAM
256byte
Interrupt
Controller
INT
1 WDT
INT
4 TBC
INT
6 8bit Timer
×6
INT
1
VLS
ECSR1～3
DSR/CSR
PC
BUS
Controller
INT
1
INT
1
INT
5
Program
Memory
(Flash)
6kbyte
UART
PWM
GPIO
RXD0
TXD0*
PWMC*
PA0 to PA2
PB0 to PB7
Figure 2 ML610Q102 Block Diagram
5/21
5 Page 
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage 1
Power supply voltage 2
Input voltage
Output voltage
Output current 1
Power dissipation
Storage temperature
Symbol
VDD
VPP
VIN
VOUT
IOUT1
PD
TSTG
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
⎯
RECOMMENDED OPERATING CONDITIONS
Parameter
Operating temperature
Symbol
TOP
Condition
⎯
Operating voltage
Operating frequency (CPU)
VDD
⎯
fOP VDD = 2.7V to 5.5V
OPERATING CONDITIONS OF FLASH MEMORY
Parameter
Symbol
Condition
Operating temperature
TOP
At write/erase
Operating voltage
VDD At write/erase
VPP At write/erase
Rewrite counts
Data retention*1
CEP
YDR
―
―
*1 : However, please keep active time of the flash memory from exceeding ten years.
Vpp pin has internal pull-down resistor.
FEDL610Q101 -01
ML610Q101/ML610Q102
Rating
−0.3 to +7.0
−0.3 to +9.5
−0.3 to VDD+0.3
−0.3 to VDD+0.3
−12 to +11
0.5
−55 to +150
(VSS = 0V)
Unit
V
V
V
V
mA
mW
°C
Range
−40 to +85
2.7 to 5.5
30k to 8.4M
(VSS = 0V)
Unit
°C
V
Hz
(VSS=0V)
Rating
Min. Typ. Max.
Unit
0 ― +40 °C
4.5 ― 5.5
V
7.7 ― 8.3
― ― 80 cycles
10 ― ― years
11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ML610Q102.PDF ] | |
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