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PDF ML610Q422 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q422 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML610Q422 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ML610Q421/ML610Q422
8-bit Microcontroller with a Built-in LCD driver
FEDL610Q421-03
Issue Date: Feb.9, 2015
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit
successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
0.24 4µs (@4.096 MHz system clock)
• Internal memory
− Internal 32KBbyte Flash ROM (16K×16 bits) (including unusable 1KByte TEST area)
− Internal 1KByte Data RAM (1024×8 bits), 1KByte Display Allocation RAM (1024 x 8bit)
− Internal 100Byte RAM for display
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 20 maskable interrupt sources (Internal sources: 16, External sources: 4)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
1/37
1 page  
BLOCK DIAGRAM
ML610Q421 Block Diagram
Figure 1 show the block diagram of the ML610Q421.
"*" indicates the secondary function of each port.
FEDL610Q421-03
ML610Q421/ML610Q422
VDD
VSS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
VDDL
VDDX
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
AVDD
AVSS
VREF
AIN0, AIN1
EPSW1～3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U8/100)
GREG
0～15
ELR1～3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
RESET &
TEST
OSC
Power
INT
1
RC-ADC
×2
RAM
1024byte
Interrupt
Controller
INT
1
WDT
INT
4
TBC
INT
1
1kHzTC
Capture
×2
INT
4 8bit Timer
×4
ECSR1～3
DSR/CSR
PC
BUS
Controller
INT
1
INT
1
INT
1
INT
1
INT
1
INT
5
Program
Memory
(Flash)
32Kbyte
SSIO
UART
I2C
PWM
Melody
GPIO
12bit-ADC
INT
1
Display Allocation
RAM 1024Byte
LCD
Driver
BLD
Display RAM
100Byte
LCD
BIAS
VPP
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
SDA*
SCL*
PWM0*
MD0*
NMI
P00 to P03
P10 to P11
P20 to P22
P30 to P35
P40 to P47
PA0 to PA7
COM0 to COM7
SEG0 to SEG49
VL1, VL2, VL3, VL4
C1, C2, C3, C4
Figure 1 ML610Q421 Block Diagram
5/37
5 Page 
PAD COORDINATES
ML610Q421 Pad Coordinates
FEDL610Q421-03
ML610Q421/ML610Q422
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pad
Name
VPP
RESET_N
P42
P43
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
Vss
VDDX
XT0
XT1
Vss
NMI
VL1
VL2
VL3
VL4
C1
C2
C3
C4
P00
P01
P02
P03
Vss
P10
P11
VDD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
X
(μm)
-1240
-1160
-1080
-1000
-920
-840
-760
-680
-600
-520
-440
-360
-280
-200
-120
-40
40
120
200
360
520
600
680
840
920
1000
1080
1160
1240
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
Y
(μm)
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1240
-1160
-1040
-960
-880
-800
-660
-580
-420
-340
-240
-160
-80
0
80
160
240
320
400
480
560
Table 1 ML610Q421 Pad Coordinates
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pad
Name
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
PA0
PA1
PA2
X
(μm)
1384
1384
1384
1384
1384
1384
1384
1384
1160
1080
1000
920
840
760
680
600
520
440
360
280
200
120
40
-40
-120
-200
-280
-360
-440
-520
-600
-680
-760
-840
-920
-1000
-1080
-1160
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
Y
(μm)
640
720
800
880
960
1040
1120
1200
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1200
1120
1040
960
880
800
720
640
560
480
400
320
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
Chip Center: X=0,Y=0
Pad
Name
XY
(μm) (μm)
PA3
PA4
PA5
PA6
PA7
P20
P21
P22
P40
P41
Vss
AVss
VREF
AIN0
AIN1
AVDD
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
240
160
80
0
-80
-200
-280
-360
-440
-520
-600
-680
-840
-920
-1092
-1172
11/37
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML610Q422.PDF ] | |
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