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PDF ML610Q429 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q429 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML610Q429 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ML610Q428/ML610Q429
8-bit Microcontroller with a Built-in LCD driver
FEDL610Q428-04
Issue Date: May.15, 2015
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD
driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
0.24 4µs (@4.096 MHz system clock)
• Internal memory
− Internal 48KByte Flash ROM (24K×16 bits) (including unusable 1KByte TEST area)
− Internal 3KByte Data RAM (3072×8 bits), 1KByte Display Allocation RAM (1024 x 8bit)
− Internal 192-byte RAM for display
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 27 maskable interrupt sources (Internal sources: 19, External sources: 8)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 2 channels (16-bit configuration available)
• 1 kHz timer
− 10 Hz/1 Hz interrupt function
1/34
1 page  
BLOCK DIAGRAM
ML610Q428 Block Diagram
Figure 1 show the block diagram of the ML610Q428.
"*" indicates the secondary function of each port.
FEDL610Q428-04
ML610Q428/ML610Q429
VDD
VSS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
VDDL
VDDX
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
EPSW1～3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U8/100)
GREG
0～15
ELR1～3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
RESET &
TEST
RAM
2048byte
OSC
Interrupt
Controller
INT
1
WDT
Power
INT
1
RC-ADC
×2
INT
8
TBC
INT
1
1kHzTC
INT
2 8bit Timer
×2
ECSR1～3
DSR/CSR
PC
BUS
Controller
INT
1
INT
1
INT
1
INT
3
INT
1
INT
5
Program
Memory
(Flash)
48Kbyte
SSIO
UART
I2C
PWM
×3
Melody
GPIO
Display Allocation
RAM 1KByte
BLD
Display RAM
192Byte
LCD
Driver
LCD
BIAS
VPP
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
SDA*
SCL*
PWM0* to PWM2*
MD0*
NMI
P00 to P03
P10 to P11
P20 to P22
P30 to P35
P40 to P47
COM0 to COM23
SEG0 to SEG57
VL1, VL2, VL3, VL4
C1, C2, C3, C4
Figure 1 ML610Q428 Block Diagram
5/34
5 Page 
PIN LIST
PAD No.
Primary function
Secondary function
Q429 Q428 Pin name I/O
Function
Pin name I/O
8,114 8,114
Vss
Negative power supply
pin
11,112 11,112 VDD
Positive power supply
pin
113 113
Power supply pin for
VDDL
internal logic (internally
generated)
115 115
VDDX
Power supply pin for
low-speed oscillation
(internally generated)
99 99
VPP
Power supply pin for
Flash ROM
120 120
Power supply pin for
VL1 LCD bias (internally
generated)
121 121
Power supply pin for
VL2 LCD bias (internally
generated)
122 122
Power supply pin for
VL3 LCD bias (internally
generated)
123 123
Power supply pin for
VL4 LCD bias (internally
generated)
124 124
Capacitor connection
C1 pin for LCD bias
generation
125 125
Capacitor connection
C2 pin for LCD bias
generation
11
Capacitor connection
C3 pin for LCD bias
generation
22
Capacitor connection
C4 pin for LCD bias
generation
111 111
TEST
Input/output pin for
I/O testing
100 100 RESET_N I Reset input pin
Low-speed clock
116 116 XT0 I oscillation pin
117 117
XT1
O
Low-speed clock
oscillation pin
77
NMI
Non-maskable interrupt
I pin
Input port, External
3 3 P00/EXI0 I interrupt 0 input
Input port, External
4 4 P01/EXI1 I interrupt 1 input
P02/EXI2
Input port, External
interrupt 2, UART0
5
5
/RXD0
I receive, PWM2
/P2CK
external clock input
Function
Input port, External
6 6 P03/EXI3 I interrupt 3
90
Input port, External
P04/EXI4 I/O interrupt 4
Input port, External
91 P05/EXI5 I/O interrupt 5
92
Input port, External
P06/EXI6 I/O interrupt 6
93 P07/EXI7 I/O Input port, External
FEDL610Q428-04
ML610Q428/ML610Q429
Tertiary function
Pin name I/O
Function
11/34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML610Q429.PDF ] | |
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