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PDF THB6064AH Data sheet ( Hoja de datos )
| Número de pieza | THB6064AH | |
| Descripción | PWM Chopper-Type bipolar Stepping Motor Driver IC | |
| Fabricantes | DARXTON | |
| Logotipo |  |
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THB6064AH
THB6064AH
THB6064AH
PWM Chopper-Type bipolar
Stepping Motor Driver IC
The THB6064AH is a PWM chopper-type sinusoidal micro-step
bipolar stepping motor driver IC.
It supports 8 kind of excitation modes and forward/reverse mode and
is capable of low-vibration, high-performance drive of 2-phase bipolar
type stepping motors using only a clock signal.
THB6064AH
Features
x Single-chip bipolar sinusoidal micro-step stepping motor driver
x Uses high withstand voltage BiCD process:
Ron (upper ҙ lower) 0.4 : (typ.)
Weight:
HZIP25-P-1.27: 9.86 g (typ.)
x Forward and reverse rotation control available
x Selectable phase drive (1/2,1/8,1/10, 1/16, 1/20, 1/32, 1/40, 1/64 step)
x High output withstand voltage: VDSS 50 V
x High output current: IOUT 4.5 A (peak)
x Packages: HZIP25-P-1.27
x Output monitor pins (DOWN / ALERT)
x Equipped with reset and enable pins
x Built-in thermal shutdown(TSD) and over-current detection(ISD) circuit
TheTHB6064AH is a Sn-Ag plated product including Pb.
The following conditions apply to solderability:
*Solderability
1. Use of Sn-37Pb solder bath
*solder bath temperature 230°C
*dipping time 5 seconds
*number of times once
*use of R-type flux
2. Use of Sn-3.0Ag-0.5Cu solder bath
*solder bath temperature 245°C
*dipping time 5 seconds
*the number of times once
*use of R-type flux
These ICs are highly sensitive to electrostatic discharge. When handling them, ensure that the environment is protected
against electrostatic discharge. Ensure also that the ambient temperature and relative humidity are maintained at
reasonable level.
ESD(Electro-Static Discharge) 㧦 HBM±1500V, MM±150V (design target value)
1 2011-05-11
1 page  
THB6064AH
THB6064AH
Electrical Characteristics (Ta 25°C, VDD 5V, VM 24V)
Control circuit
Characteristic
Symbol
Test Condition
Min Typ. Max Unit
Input voltage
High
Low
Input hysteresis voltage
Input current
VDD supply current
VM supply current
Vref input
circuit
Input current
Divider ratio
Minimum CLK pulse width
VIN (H)
VIN (L)
VH
M1, M2, M3, CW/CCW, CLK,
RESET, ENABLE, DCY1, DCY2
2.0 VDD
V
0.2
0.8
400 mV
IIN (H)
IIN (L)
M1, M2, M3, CW/CCW, CLK,
RESET, ENABLE, DCY1, DCY2
VIN 5.0 V
VIN 0 V
55 80 PA
1
IDD1
IDD2
IDD3
IM1
IM2
IIN(ref)
Vref/VNF
Output open,
RESET: H, ENABLE: H
M1:L, M2:L, M3:L (1/2-step mode)
RESET: L, ENABLE: H
RESET: L, ENABLE: L
RESET: H/L, ENABLE: L
RESET: H/L, ENABLE: H
Vref=3.0V
Maximum current : 100%
37
mA
27
27
0.5 ( )
mA
1 ()
1 PA
3
tCLK
2.3 Ps
Output residual voltage
TSD operation temperature(Note)
TSD hysteresis (Note)
VOL DOWN
IOL 1 mA
VOL ALERT
TSD
(Design target value)
TSDhys (Design target value)
0.5 V
170
40
°C
°C
Oscillation frequency
fosc1
using built-in capacitor and resistor 50
100 200 kHz
Oscillation frequency
fosc2
ROSC 51kȍ
2.6 4 5.4 MHz
Oscillation
circuit for
CLK monitor
Detection CLK
frequency
fdetect using built-in capacitor and resistor 1.0 2.0 4.0 Hz
Note: Pre-shipment testing is not performed.
Output Block
Characteristic
Symbol
Test Condition
Output ON resistor
Output transistor switching
characteristics
Output leakage current
Upper side
Lower side
RonH + RonL IOUT 4 A
tr RL 2 :, VNF 0 V,
tf CL 15 pF
ILH
VM 50 V
ILL
Min Typ. Max Unit
0.4 0.6 :
1.5
0.5
Ps
ʊ
5
PA
ʊ
5
5 2011-05-11
5 Page 
THB6064AH
THB6064AH
Current Waveform in Fast Decay Mode
After the output current to the load reaches the current value specified by RNF, torque or other means, the output
current to the load will be fed back to the power supply fully in Fast Decay mode
20% fast DECAY MODE
OSC Pin
Internal
Waveform
Predefined
Cu⸳rreቯnt㔚Lᵹev୯el
IOUT
fchop
NF
fchop
fchop
MDT
Predefined
⸳ቯ㔚ᵹ୯
Current Level
NF
MDT
CLK Signal Input
The OSC counter is reset here.
Switches to Charge mode briefly
When the CLK signal is asserted, the Chopping Counter (OSC Counter) is forced to reset at the next rising edge
of the OSC signal.
As a result, the response to input data is faster compared to methods in which the counter is not reset.
The delay time that is theoretically determined by the logic circuit is one OSC cycle.
After the OSC Counter is reset by the CLK signal input, the current control mode is invariably switched to Charge
mode briefly for current sensing.
Note: Even in Fast Decay mode, the current control mode is invariably switched to Charge mode briefly for
current sensing.
11 2011-05-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet THB6064AH.PDF ] | |
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