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PDF CY621472G Data sheet ( Hoja de datos )
| Número de pieza | CY621472G | |
| Descripción | 4-Mbit (256K words x 16 bit) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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PRELIMINARY
CY62147G, CY621472G
CY62147GE MoBL®
4-Mbit (256K words × 16 bit) Static RAM with
Error-Correcting Code (ECC)
16-Mbit (1 M words × 16 bit / 2 M words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed: 45 ns/55 ns
■ Ultra-low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
■ Embedded ECC for single-bit error correction[1]
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Functional Description
CY62147G and CY62147GE are high-performance CMOS
low-power (MoBL) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62147GE device includes an
ERR pin that signals an error-detection and correction event
during a read cycle.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as low and CE2 as HIGH.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O15 and
address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE1 HIGH/CE2 LOW for a dual chip enable device), or
control signals are deasserted (OE, BLE, BHE).
The device also has a unique Byte Power down feature, where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enables, thereby saving power.
On the CY62147GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)[1]. See the Truth
Table – CY62147G/CY62147GE on page 16 for a complete
description of read and write modes.
The logic block diagrams are on page 2.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-92847 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 3, 2015
1 page  
PRELIMINARY
CY62147G, CY621472G
CY62147GE MoBL®
Pin Configuration – CY62147GE
Figure 4. 48-ball VFBGA Pinout (Dual Chip Enable with ERR) Figure 5. 48-ball VFBGA Pinout (Single Chip Enable with ERR)
– CY62147GE[3, 4]
– CY62147GE[3, 4]
12 34 56
12 34 56
BLE OE A0 A1 A2 CE2
I/O8 BHE A3 A4 CE1 I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 VCC
VCC I/O12 ERR A16 I/O4 Vss
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
BLE OE A0 A1 A2 NC
I/O8 BHE A3 A4 CE I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 VCC
VCC I/O12 ERR A16 I/O4 Vss
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
Figure 6. 44-pin TSOP II Pinout (Single Chip Enable with ERR) – CY62147GE[3, 4]
A
B
C
D
E
F
G
H
A4
A3
A2
A1
A0
/ CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1 44 A5
2 43 A6
3 42 A7
4 41 /OE
5 40 / BHE
6 39 1 / BLE
7 38 I/O15
8 37 I/O14
9 36 I/O13
10 35 I/O12
11 34 VSS
12 44- TSOP-II 33 VCC
13 32 I/O11
14 31 I/O10
15 30 I/O9
16 29 I/O8
17 28 ERR
18 27 A8
19 26 A9
20 25 A10
21 24 A11
22 23 A12
Notes
3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
4. ERR is an output pin.
Document Number: 001-92847 Rev. *D
Page 5 of 21
5 Page 
PRELIMINARY
CY62147G, CY621472G
CY62147GE MoBL®
AC Switching Characteristics
Parameter [18, 19]
Description
READ CYCLE
tRC
tAA
tOHA
Read cycle time
Address to data valid / Address to ERR valid
Data hold from address change / ERR hold from
address change
tACE CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR
valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
OE LOW to data valid / OE LOW to ERR valid
OE LOW to Low impedance[19, 21]
OE HIGH to HI-Z[19, 20, 21]
CE1 LOW and CE2 HIGH to Low impedance[19, 21]
CE1 HIGH and CE2 LOW to HI-Z[19, 20, 21]
CE1 LOW and CE2 HIGH to power-up[21]
CE1 HIGH and CE2 LOW to power-down[21]
tDBE
BLE / BHE LOW to data valid
tLZBE
BLE / BHE LOW to Low impedance[19, 21]
tHZBE
BLE / BHE HIGH to HI-Z[19, 20, 21]
WRITE CYCLE[22, 23]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Write cycle time
CE1 LOW and CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE / BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to HI-Z[19, 20, 21]
WE HIGH to Low impedance[19, 21]
45 ns
Min Max
45 –
– 45
10 –
– 45
– 22
5–
– 18
10 –
– 18
0–
– 45
– 45
5–
– 18
45 –
35 –
35 –
0–
0–
35 –
35 –
25 –
0–
– 18
10 –
55 ns
Min Max
Unit
55 – ns
– 55 ns
10 – ns
– 55 ns
– 25 ns
5 – ns
– 18 ns
10 – ns
– 18 ns
0 – ns
– 55 ns
– 55 ns
5 – ns
– 18 ns
55 – ns
45 – ns
45 – ns
0 – ns
0 – ns
40 – ns
45 – ns
25 – ns
0 – ns
– 20 ns
10 – ns
Notes
18. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
21. These parameters are guaranteed by design.
22. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
23. The minimum pulse width in write cycle No 3 (WE Controlled, OE low) should be equal to sum of tSD and tHZWE.
Document Number: 001-92847 Rev. *D
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CY621472G.PDF ] | |
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