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PDF SN9P701-00X Data sheet ( Hoja de datos )
| Número de pieza | SN9P701-00X | |
| Descripción | OPTICAL ID IMAGE Decoder | |
| Fabricantes | SONiX | |
| Logotipo |  |
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松翰科技股份有限公司
SONiX TECHNOLOGY CO., LTD.
Preliminary
SN9P701-00X
OPTICAL ID IMAGE Decoder [ 2nd generation ]
- two_wire_interface version
1. General Description
SN9P701 is the second generation of OID decoder. It is designed for implementing
SONiX newly developed D.H.R.T. Technology (Data Hiding & Retrieving
Technology), which integrates the solution that includes CMOS sensor interface, image
pattern recognizing engine, voltage regulator, RC oscillator and retrieved index output
interface.
2. Feature of SN9P701
- Support dot pattern format : OID_Code_v2
- Core voltage operation range : 3.0V ~ 3.6V ( Reference design )
- Regulator input : 3.6V ~5.0V ( Reference design )
- Low power dissipation : 5mA (typ)
- Shot down current : <10uA
- Embedded 16 bit-DSP for sensor control and image pattern recognition
- Light source timing control
- Built-in voltage regulator
- Built-in 16Mhz RC type oscillator ( not recommended in RF/IR version )
- Built-in low battery detection
- Bi-directions communication in two wire serial interface
- Output Optical_ID in two_wire_serial_interface
( Please refer to two_wire_interface_v2.pdf )
- 48 pin LQFP package.
3. Feature of OID_Code_V2
OID_Code_V2 is the 2nd generation of dot pattern used in OID system.
- Dimension of single dot pattern : 1.3mm x 1.3mm
- Number of index : 65,536（can extend to 262,144）
- Low visual artifact
- Low visual fixed pattern noise
- Suggested paper type :art coated paper, mid-grade paper*
1
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
SONiX TECHNOLOGY CO., LTD.
E-mail: [email protected]
V1.0 ,MAR. 2006
1 page  
松翰科技股份有限公司
SONiX TECHNOLOGY CO., LTD.
Preliminary
SN9P701-00X
31 KEY0
32 BAT_SW
33 BAT_DET
34 RST
I KEY0 input（internal pull down）
O Switch for battery voltage detection
Low voltage detection input.
Voltage applied to pin BAT_DET is compared with internal threshold
I
level (VDD3)／3 and reports result via two wire interface every 10
sec.
B Chip reset（internal pull down）
35 TEST
36 KEY2
37 VDD
38 GND
39 SEN_CMD
40 SEN_CLK
41 SEN_D0
42 SEN_D1
I Test pin for IC test, please connect to ground
I KEY2 input（internal pull down）, connect to ground if not used
I Digital VDD, 3.3V
P Digital ground
B Sensor control interface, connect to SN9S102C directly
O Sensor clock, connect to SN9S102C directly
I Sensor image data input, connect to SN9S102C directly
I Sensor image data input, connect to SN9S102C directly
43 OP_GND
P Analog ground
44 IRED1
O Output for IRED_1 control
45 IRED_FEB1 I Voltage feedback for IRED1 control
46 IRED_FEB0 I Voltage feedback for IRED0 control
47 IRED0
O Output for IRED_0 control
48 OP_VDD
P Analog VDD, 3.3V
5
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
SONiX TECHNOLOGY CO., LTD.
E-mail: [email protected]
V1.0 ,MAR. 2006
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SN9P701-00X.PDF ] | |
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