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PDF CY8C4125LQI-483 Data sheet ( Hoja de datos )
| Número de pieza | CY8C4125LQI-483 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
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PSoC® 4: PSoC 4100 Family
Datasheet
Programmable System-on-Chip (PSoC®)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system
controllers with an ARM® Cortex™-M0 CPU. It combines programmable and re-configurable analog and digital blocks with flexible
automatic routing. The PSoC 4100 product family, based on this platform, is a combination of a microcontroller with digital program-
mable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing
peripherals. The PSoC 4100 products will be fully upward compatible with members of the PSoC 4 platform for new applications and
design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Sub-system
■ 24-MHz ARM Cortex-M0 CPU with single-cycle multiply
■ Up to 32 kB of flash with Read Accelerator
■ Up to 4 kB of SRAM
Programmable Analog
■ Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability
■ 12-bit 806 Ksps SAR ADC with differential and single-ended
modes and Channel Sequencer with signal averaging
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■ Two low-power comparators that operate in Deep Sleep
Low Power 1.71-V to 5.5-V operation
■ 20-nA Stop Mode with GPIO pin wakeup
■ Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
Capacitive Sensing
■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and water tolerance
■ Cypress supplied software component makes capacitive
sensing design easy
■ Automatic hardware tuning (SmartSense™)
Segment LCD Drive
■ LCD drive supported on all pins (common or segment)
■ Operates in Deep Sleep mode with 4 bits per pin memory
Serial Communication
■
Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
Timing and Pulse-Width Modulation
■ Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals for motor drive and
other high reliability digital logic applications
Up to 36 Programmable GPIOs
■ 48-pin TQFP, 44-pin TQFP, 40-pin QFN, and 28-pin SSOP
packages.
■ Any GPIO pin can be CapSense, LCD, analog, or digital
■ Drive modes, strengths, and slew rates are programmable
PSoC Creator Design Environment
■ Integrated Development Environment provides schematic
design entry and build (with analog and digital automatic
routing)
■ Applications Programming Interface (API Component) for all
fixed-function and programmable peripherals
Industry Standard Tool Compatibility
■ After schematic entry, development can be done with
ARM-based industry-standard development tools
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-87220 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 8, 2015
1 page  
PSoC® 4: PSoC 4100 Family
Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in PSoC 4100 is part of the 32-bit MCU
subsystem, which is optimized for low power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC), which can wake the processor up
from Deep Sleep mode allowing power to be switched off to the
main processor when the chip is in Deep Sleep mode. The
Cortex-M0 CPU provides a Non-Maskable Interrupt input (NMI),
which is made available to the user when it is not in use for
system functions requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG; the debug
configuration used for PSoC 4100 has four break-point
(address) comparators and two watchpoint (data) comparators.
Flash
PSoC 4100 has a flash module with a flash accelerator tightly
coupled to the CPU to improve average access times from the
flash block. The flash block is designed to deliver 0 wait-state
(WS) access time at 24 MHz. Part of the flash module can be
used to emulate EEPROM operation if required.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
Power System
The power system is described in detail in the section Power on
page 13. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low-voltage detect (LVD)). The
PSoC 4100 operates with a single external supply over the range
of 1.71 V to 5.5 V and has five different power modes, transitions
between which are managed by the power system. PSoC 4100
provides Sleep, Deep Sleep, Hibernate, and Stop low-power
modes.
Clock System
The PSoC 4100 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that no metastable conditions occur.
The clock system for PSoC 4100 consists of the internal main
oscillator (IMO) and the internal low-power oscillator (ILO) and
provision for an external clock.
Figure 3. PSoC 4100 MCU Clocking Architecture
IMO
EXTCLK
HFCLK
ILO LFCLK
HFCLK
Prescaler
SYSCLK
UDB
Dividers
Analog
Divider
Peripheral
Dividers
UDBn
SAR clock
PERXYZ_CLK
The HFCLK signal can be divided down (see PSoC 4100 MCU
Clocking Architecture) to generate synchronous clocks for the
analog and digital peripherals. There are a total of 12 clock
dividers for PSoC 4100, each with 16-bit divide capability. The
analog clock leads the digital clocks to allow analog events to
occur before digital clock-related noise is generated. The 16-bit
capability allows a lot of flexibility in generating fine-grained
frequency values and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4100. It is trimmed during testing to achieve the specified
accuracy. Trim values are stored in nonvolatile latches (NVL).
Additional trim settings from flash can be used to compensate for
changes. The IMO default frequency is 24 MHz and it can be
adjusted between 3 MHz to 24 MHz in steps of 1 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power oscillator, which is primarily used to
generate clocks for peripheral operation in Deep Sleep mode.
ILO-driven counters can be calibrated to the IMO to improve
accuracy. Cypress provides a software component, which does
the calibration.
Document Number: 001-87220 Rev. *D
Page 5 of 39
5 Page 
PSoC® 4: PSoC 4100 Family
Datasheet
Figure 5. 48-Pin TQFP Pinout
Figure 6. 44-pin TQFP Part Pinout
VSS
(GPIO) P2[ 0]
(GPIO) P2[1]
(GPIO) P2[2]
(GPIO) P2[3]
(GPIO) P2[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
VSS
( GPIO) P3[0]
1
2
3
4
5
6
7
8
9
10
11
TQFP
(Top View)
33 VCCD
32 XRES
31 (GPIO) P0[7]
30 (GPIO) P0[6]
29 (GPIO) P0[5]
28 (GPIO) P0[4]
27 (GPIO) P0[3]
26 (GPIO) P0[2]
25 (GPIO) P0[1]
24 ( GPIO) P0[0]
23 ( GPIO) P4[3]
Document Number: 001-87220 Rev. *D
Page 11 of 39
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