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PDF ADUC7034 Data sheet ( Hoja de datos )
| Número de pieza | ADUC7034 | |
| Descripción | Battery Sensor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADUC7034 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Preliminary Technical Data
Integrated Precision Battery Sensor
for Automotive
ADuC7034
FEATURES
High precision ADCs
Dual channel, simultaneous sampling, 16-bit, Σ-∆ ADCs
Programmable ADC throughput from 1 Hz to 8 kHz
On-chip 5 ppm/°C voltage reference
Current channel
Fully differential, buffered input
Programmable gain from 1 to 512
ADC input range: −200 mV to +300 mV
Digital comparators, with current accumulator feature
Voltage channel
Buffered, on-chip attenuator for 12 V battery inputs
Temperature channel
External and on-chip temperature sensor options
Microcontroller
ARM7TDMI® core, 16-/32-bit RISC architecture
20.48 MHz PLL with programmable divider
PLL input source
On-chip precision oscillator
On-chip low power oscillator
External (32.768 kHz) watch crystal
JTAG port supports code download and debug
Memory
32-kB Flash/EE memory, 4-kB SRAM
10,000-cycle Flash/EE endurance, 20-year Flash/EE
retention
In-circuit download via JTAG and LIN
On-chip peripherals
LIN 2.0-compatible (slave) support via UART with
hardware synchronization
Flexible wake-up I/O pin, master/slave SPI® serial I/O
9-pin GPIO port, 3× general-purpose timers
Wake-up and watchdog timers
Power supply monitor, on-chip power-on-reset
Power
Operates directly from 12 V battery supply
Current consumption
Normal mode 10 mA at 10 MHz
Low power monitor mode
Package and temperature range
48-lead, 7 mm × 7 mm LFCSP
Fully specified for −40°C to +115°C operation
APPLICATIONS
Battery sensing/management for automotive systems
FUNCTIONAL BLOCK DIAGRAM
IIN+
IIN-
VBAT
VTEMP
VREF+
VREF-
CREF
PRECISION ANALOG ACQUISITION
BUF PGA
16-BIT
Σ−∆ ADC
RESULT
DIGITAL
ACCUMULATOR COMPARATOR
MUX BUF
16-BIT
Σ−∆ ADC
TEMPERATURE
SENSOR
PRECISION
REFERENCE
2.6V LDO
PSM
POR
ARM7TDMI
MCU
20MHz
3XTIMERS
WDT
W/U TIMER
MEMORY
96KB FLASH
6KB RAM
PRECISION
OSC
LOW POWER
OSC
ON-CHIP PLL
GPIO PORT
UART PORT
SPI PORT
LIN
RESET
XTAL1
XTAL2
WU
STI
LIN/BSD
Figure 1.
Rev. Pr.A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
SPI Control Register ............................................................ 115
SPI Status Register ............................................................... 116
SPI Receive Register............................................................. 116
SPI Transmit Register .......................................................... 117
SPI Divider Register............................................................. 117
Serial Test Interface ...................................................................... 118
Serial Test Interface Key0 Register .................................... 118
Serial Test Interface Key1 Register .................................... 118
Serial Test Interface Data0 Register................................... 118
Serial Test Interface Data1 Register................................... 119
Serial Test Interface Data2 Register................................... 119
Serial Test Interface Control Register................................ 119
Serial Test Interface Output Structure .............................. 120
Using the Serial Test Interface............................................ 120
LIN (Local Interconnect Network) Interface ........................... 122
LIN MMR Description............................................................ 122
LIN Hardware Synchronization Status Register .............. 123
LIN Hardware Synchronization Control Register 0........ 124
LIN Hardware Synchronization Control Register 1........ 126
LIN Hardware Synchronization Timer0 Register............ 126
LIN Hardware Break Timer1 Register .............................. 126
LIN Hardware Interface .......................................................... 127
LIN Frame Protocol............................................................. 127
LIN Frame Break Symbol ................................................... 127
LIN Frame Synchronization Byte ...................................... 127
LIN Frame Protected Identifier.......................................... 127
ADuC7034
LIN Frame Data Byte ...........................................................127
LIN Frame Data Transmission and Reception .................127
Example LIN Hardware Synchronization Routine ..........129
LIN Diagnostics ....................................................................130
LIN Operation During Thermal Shutdown......................130
Bit Serial Device (BSD) Interface................................................131
BSD Communication Hardware Interface ............................131
BSD Related MMRs ..................................................................132
LIN Hardware Synchronization Capture Register ...........132
LIN Hardware Synchronization Compare Register .........132
BSD Communications Frame .................................................133
BSD Example Pulse Widths.................................................133
Typical BSD Program Flow .................................................133
BSD Data Reception .................................................................134
BSD Data Transmission ...........................................................134
Wake-Up from BSD Interface .................................................134
Part Identification .........................................................................135
System Serial ID Register 0..................................................135
System Serial ID Register 1..................................................135
System Assembly Lot ID ......................................................136
System Kernel Checksum ....................................................136
System Identification FEE0ADR ........................................137
Schematic .......................................................................................138
Outline Dimensions......................................................................139
Ordering Guide .........................................................................139
Rev. Pr.A | Page 5 of 142
5 Page 
Preliminary Technical Data
ADuC7034
4 Tested at gain range = 4; self-offset calibration removes this error.
5 Measured with an internal short after an initial offset calibration.
6 Measured with an internal short.
7 These numbers include internal reference temperature drift.
8 Factory calibrated at gain = 1.
9 System calibration at a specific gain range removes the error at this gain range. At that temperature
10 Includes an initial system calibration.
11 Using ADC normal mode voltage reference.
12 1 kHz update rate chop enable is achieved with ADCFLT = 0x8101; yet with chop off, ADCFLT = 0x0007.
13 Typical noise in low power modes is measured with chop enabled.
14 Voltage channel specifications include resistive attenuator input stage.
15 System calibration removes this error at that temperature.
16 RMS noise is referred to voltage attenuator input, for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 μV, scaled by the attenuator (24) yields these
input referred noise figures.
17 Valid after an initial self calibration.
18 In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV.
19 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
20 Limited by minimum/maximum absolute input voltage range.
21 Valid for a differential input less than 10 mV.
22 Measured using box method.
23 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
24 References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2.
25 Die temperature.
26 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
27 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
28 Low Power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code.
29 These numbers are not production tested, but are supported by LIN compliance testing.
30 BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and CLoad = 10 nF maximum.
31 Specified after RLIMIT of 39 Ω.
32 The MCU core is not shutdown but interrupted, and high voltage I/O pins are disabled in response to a thermal shutdown event.
33 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.
34 Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA), and REG_AVDD (ISOURCE = 1 mA).
35 Typical, additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
TIMING SPECIFICATIONS
SPI Timing Specifications
Table 2. SPI Master Mode Timing (PHASE Mode = 1)
Parameter Description
tSL SCLK low pulse width1
tSH SCLK high pulse width1
tDAV Data output valid after SCLK edge2
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge2
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
0
3 × tUCLK
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
3.5
3.5
3.5
3.5
1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD.
2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
Max
(2 × tUCLK) + (2 × tHCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. Pr.A | Page 11 of 142
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADUC7034.PDF ] | |
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