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PDF AT24C512C Data sheet ( Hoja de datos )
| Número de pieza | AT24C512C | |
| Descripción | EEPROM | |
| Fabricantes | ATMEL Corporation | |
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AT24C512C
I2C-Compatible (2-wire) Serial EEPROM
512-Kbit (65,536 x 8)
DATASHEET
Features
Low-voltage and Standard-voltage Operation
̶ VCC = 1.7V to 3.6V
̶ VCC = 2.5V to 5.5V
Internally Organized as 65,536 x 8 (512K)
I2C-Compatible (2-Wire) Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 5.5V) Compatibility
Write Protect Pin for Hardware Data Protection
128-byte Page Write Mode
̶ Partial Page Writes Allowed
Random and Sequential Read Modes
Self-timed Write Cycle (5ms Max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 40 Years
Green Package Options (Pb/Halide-free/RoHS Compliant)
̶ 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-pad UDFN,
8-ball WLCSP, and 8-ball VFBGA Packages
Die sale Options: Wafer Form and Tape and Reel Available
Description
The Atmel® AT24C512C provides 524,288 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 65,536 words of
8 bits each. The cascadable feature of the device allows up to eight devices to
share a common 2-wire bus. The device is optimized for use in many industrial
and commercial applications where low-power and low-voltage operation are
essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead
EIAJ SOIC, 8-lead TSSOP, 8-pad UDFN, 8-ball WLCSP, and 8-ball VFBGA
packages. In addition, the entire family is available in 1.7V to 3.6V and 2.5V to
5.5V versions.
Atmel-8720F-SEEPROM-AT24C512C-Datasheet_012015
1 page  
5.3 AC Characteristics
Table 5-3. AC Characteristics
Applicable over recommended operating range from TAI = -40C to +85C, VCC = 1.7V to 3.6V or 2.5V to 5.5V (where
applicable), CL = 100pF (unless otherwise noted). Test conditions are listed in Note 2.
1.7V
2.5V, 5.0V
Symbol
Parameter
Min Max Min Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
Clock Frequency, SCL
400 1000
Clock Pulse Width Low
1.3 0.4
Clock Pulse Width High
0.6 0.4
Noise Suppression Time(1)
100 50
Clock Low to Data Out Valid
0.05 0.9 0.05 0.55
Time the bus must be free before a new
transmission can start(1)
1.3
0.5
kHz
μs
μs
ns
μs
μs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode, 3.3V
0.6 0.25
μs
0.6 0.25
μs
00
μs
100 100
ns
0.3 0.3 μs
300 100 ns
0.6 0.25
μs
50 50
ns
5 5 ms
1,000,000
Write Cycles
Notes: 1. This parameter is ensured by characterization only.
2. AC measurement conditions:
RL (connects to VCC): 1.3k (2.5V, 5V), 10k (1.7V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: 50ns
Input and output timing reference voltages: 0.5VCC
AT24C512C [DATASHEET]
Atmel-8720F-SEEPROM-AT24C512C-Datasheet_012015
5
5 Page 
9. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit
in the device address word is set to one. There are three types of read operations: Current Address Read,
Random Address Read, and Sequential Read.
9.1 Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll-over during read is from the last byte of the last memory page to the first byte of
the first page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out on the SDA line. The microcontroller does not
respond with an zero, but does generate a following Stop condition.
Figure 9-1. Current Address Read
S
T
A
R
T
SDA Line
M
S
B
Device
Address
R
E
A
D
RA
/C
WK
Data
S
T
O
P
N
O
A
C
K
9.2 Random Read
A Random Read requires an initial byte write sequence to load in the data word address. This is known as a
“dummy write” operation. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another Start condition. The microcontroller
now initiates a current address read by sending a device address with the read/write select bit high. The
EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not
respond with a zero, but does generate a following Stop condition.
Figure 9-2. Random Read
S
T
A
R Device
T Address
W
R
I
T
E
SDA LINE
M
S
B
RA
/C
WK
First Word
Address
Second Word
Address
S
T
A
R
T
A LA
C SC
K BK
Device
Address
Dummy Write
R
E
A
D
RA
/C
WK
Data (n)
S
T
O
P
N
O
A
C
K
AT24C512C [DATASHEET]
Atmel-8720F-SEEPROM-AT24C512C-Datasheet_012015
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet AT24C512C.PDF ] | |
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