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PDF MMA6900KQR2 Data sheet ( Hoja de datos )
| Número de pieza | MMA6900KQR2 | |
| Descripción | High Accuracy Low g Inertial Sensor | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
High Accuracy Low g Inertial Sensor
MEMS Sensing, State Machine ASIC
The MMA690xQ is a dual axis, Low g, XY, Sensor based on Freescale’s
HARMEMS technology, with an embedded DSP ASIC, allowing for additional
processing of the digital signals.
Features
• Sensitivity in X and Y axes
• ±3.5 or ±5.0g full-scale range per axis
• AEC-Q100 qualified, Rev. G, grade 2 (-40 ≤ TA ≤ 105 °C)
• 50 Hz second order low-pass filter
• Unsigned 11-bits digital data output
• SPI-compatible serial interface
• Capture/hold input for system-wide synchronization support
• 3.3 or 5.0V single supply operation
• On-chip temperature sensor and voltage regulator
• Bi-directional internal self-test
• Minimal external component requirements
• Pb-free 16-pin QFN package
• Pulse-code modulated output available for device evaluation
Typical Applications
• With a ±3.5g or ±5.0g full scale range, the newly designed, high accuracy
sensor, enables Electronic Stability Control (ESC) designers to
accommodate higher original signal noise level without sacrificing resolution.
• Tilt Measurement
• Electronic Parking Brake
ORDERING INFORMATION
Device Name
Range
Shipping
MMA6900(K)Q
MMA6901(K)Q
±3.5 g
±5.0 g
Tubes
MMA6900(K)QR2
MMA6901(K)QR2
±3.5 g
±5.0 g
Tape and Reel
“K” suffix indicates the device is manufactured with an alternate silicon sourcing
MMA690xQ
Rev 2.0, 11/2010
MMA690xQ
DUAL AXIS SPI
INERTIAL SENSOR
Bottom View
16-PIN QFN
98ASA10571D
CASE 1477-02
Top View
16 15 14 13
CREF 1
12 PCM_Y
CREF 2
11 CAP/HOLD
VCC 3
10 DIN
VSS 4
9 VPP
5678
PIN CONNECTIONS
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc. 2010. All rights reserved.
1 page  
1.4.13 PCM_X, PCM_Y
MMA690xQ provides the option for a Pulse Code Modulated (PCM) output function. The PCM output is activated when
PCM_EN is set in the DEVCTL register. When the PCM function is enabled, the upper nine bits of the 11-bit scaled acceleration
values are used to generate PCM signals proportional to incident respective acceleration, at 250 ns resolution. A simplified block
diagram of the PCM output is shown in Figure 1-4.
OUTPUT SCALING
OC[9:1]
9
A CARRY
9-BIT ADDER
B SUM
9
fCLK = 4.0 MHz
9
PCM_X/PCM_Y
DQ
DQ
DQ
CLCKLDDKFDFFDFFDFFFDFFFF
Q
Q
Q
Q
Q
Q
CLK FF
CLK FF
CLK FF
CLK
CLK
CLK
CLK
Figure 1-4 PCM Output Function Block Diagram
Sensors
Freescale Semiconductor
MMA690xQ
5
5 Page 
2.1.5.3 Temperature Fault Flag (TF)
This flag is set if the value reported by the on-chip temperature sensor exceeds specified limits. TF may be cleared by writing
a logic ‘1’ value to the CE bit in DEVCTL, provided that the fault condition is no longer detected.
2.1.5.4 Device Reset Flag (DEVRES)
This flag is set during device initialization. A logic ‘1’ must be written to the CE bit in the Device Control register (DEVCTL) to
clear this bit. Except when Communications Protocol is active, this bit must be explicitly cleared following reset before accelera-
tion results can be read from MMA690xQ.
2.1.6 Counter Register (COUNT)
This read-only register provides the value of a free-running 8-bit counter derived from the primary oscillator. A five-bit prescaler
divides the 4.0 MHz primary oscillator frequency by 32. Thus, the value in the register increases by one count every 8.0 μs, and
the counter rolls over every 2.048 ms.
Table 2-8 Counter Register
Location
Address
Register
$11 COUNT
7
COUNT[7]
6
COUNT[6]
5
COUNT[5]
Bit Function
43
COUNT[4] COUNT[3]
2
COUNT[2]
1
COUNT[1]
0
COUNT[0]
2.1.7 Acceleration Result Registers
These read-only registers contain acceleration results produced by the DSP. The values in these registers are frozen by either
of two events:
• CAP/HOLD input at logic high level
• CS input at logic low level
Acceleration result registers are provided for each axis. ACC_X11L/ACC_X11H and ACC_Y11L/ACC_Y11H provide 11-bit re-
sults. Updates to ACC_X11L/ACC_X11H and ACC_Y11L/ACC_Y11H are halted upon reading the lower-byte register of either
pair until the upper-byte register is read. There is no requirement to manipulate CAP/HOLD when reading ACC_X11L/ACC_X11H
or ACC_Y11L/ACC_Y11H, however ACC_X11H or ACC_Y11H must be read after reading ACC_X11L or ACC_Y11L, respective-
ly, or further updates to the register pair will not occur.
Table 2-9. X-Axis Acceleration Result Registers
Location
Address
Register
7
6
$24 ACC_X11L ACC_X[7] ACC_X[6]
$25 ACC_X11H 0
0
5
ACC_X[5]
0
Bit Function
43
ACC_X[4] ACC_X[3]
00
2
ACC_X[2]
ACC_X[10]
1
ACC_X[1]
ACC_X[9]
0
ACC_X[0]
ACC_X[8]
Table 2-10. Y-Axis Acceleration Result Registers
Location
Address
Register
7
6
5
$26 ACC_Y11L ACC_Y[7] ACC_Y[6] ACC_Y[5]
$27 ACC_Y11H
0
0
0
Bit Function
43
ACC_Y[4] ACC_Y[3]
00
2
ACC_Y[2]
ACC_Y[10]
1
ACC_Y[1]
ACC_Y[9]
0
ACC_Y[0]
ACC_Y[8]
Sign extension is applied to the upper five bits of ACC_X11H and ACC_Y11H. If an error condition exists, the reserved
value 0 will be read in place of 11-bit acceleration data.
Sensors
Freescale Semiconductor
MMA690xQ
11
11 Page | ||
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