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PDF SSD2805 Data sheet ( Hoja de datos )
| Número de pieza | SSD2805 | |
| Descripción | MIPI Master Bridge | |
| Fabricantes | SOLOMON | |
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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD2805
Advance Information
MIPI Master Bridge
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD2805
Rev 1.1 P 1/38 Apr 2011
Copyright © 2011 Solomon Systech Limited
1 page  
TABLES
TABLE 3-1: ORDERING INFORMATION.................................................................................................................................8
TABLE 6-1: HOST INTERFACE PINS MULTIPLEXING SCHEME ...........................................................................................16
TABLE 6-2: MCU MODE INTERFACE SIGNALS .................................................................................................................17
TABLE 6-3: RGB MODE INTERFACE SIGNALS ..................................................................................................................17
TABLE 7-1: MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS) ..................................................................................20
TABLE 8-1: RECOMMENDED OPERATING CONDITIONS .....................................................................................................21
TABLE 9-1: DC CHARACTERISTICS ...................................................................................................................................22
TABLE 9-2: HS TRANSMITTER DC CHARACTERISTICS......................................................................................................23
TABLE 9-3: LP TRANSMITTER DC CHARACTERISTICS ......................................................................................................23
TABLE 9-4: LP RECEIVER DC CHARACTERISTICS .............................................................................................................23
TABLE 10-1: HS TRANSMITTER AC CHARACTERISTICS....................................................................................................24
TABLE 10-2: LP TRANSMITTER AC CHARACTERISTICS ....................................................................................................24
TABLE 10-3: LP RECEIVER AC CHARACTERISTICS ...........................................................................................................24
TABLE 10-4: 6800 MCU INTERFACE TIMING ...................................................................................................................25
TABLE 10-5: 8080 MCU INTERFACE TIMING CHARACTERISTICS .....................................................................................26
TABLE 10-6: SPI INTERFACE TIMING CHARACTERISTICS..................................................................................................28
TABLE 10-7: RGB INTERFACE TIMING CHARACTERISTICS ...............................................................................................31
TABLE 10-8: RESET TIMING ............................................................................................................................................32
TABLE 10-9: TX_CLK TIMING CHARACTERISTICS...........................................................................................................32
SSD2805
Rev 1.1 P 5/38
Apr 2011
Solomon Systech
5 Page 
5.1.6 Internal Long and Short Buffer
The internal buffers serve as temporary storage for incoming data from the host processor.
After a complete packet is written into the buffer, the SSD2805 will send out the packet.
5.1.7 D-PHY Controller
The D-PHY Controller is in charge of the communication with the Analog Transceiver.
During transmission, it receives data from PPU and informs the analog transmitter how to
transmit. During reception, it receives data from analog receiver and passes the data to the
PPU for further processing. At the same time, it is also performing the handshaking process,
such as, bus turn around and switching between different modes.
5.1.8 Analog Transceiver
The Analog Transceiver is front-end for signal communication with MIPI slave. High speed
parallel data from D-PHY controller is serialized and transmitted by the high speed
transmitter. For control operation, low power transmitter and receiver are used while
contention detection is implemented for checking the state conflict.
5.1.9 PLL
The PLL uses either the TX_CLK or the PCLK as reference clock source to generate
operating clock for the whole system.
When powering up SSD2805, the PLL is in sleep mode. The system will operate at TX_CLK
until PLL is locked.
In HS mode, the PLL output clock is used to generate the clock and data on the MIPI lane.
User shall program the PLL such that its output frequency is the same as the data rate
required on each data lane.
Refer to SSD2805 Application Note for details in programming the PLL.
TX_ CLK
PCLK
PLL
CSS
Operating clock
Lock
Figure 5-1: SSD2805 Clocking Scheme
5.2 Interface Configuration
The SSD2805 supports two interface configurations:
• MCU interface
• RGB + SPI interface.
Multiple displays can be supported in both configurations.
SSD2805
Rev 1.1 P 11/38
Apr 2011
Solomon Systech
11 Page | ||
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| PDF Descargar | [ Datasheet SSD2805.PDF ] | |
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